公开(公告)号：US20240160364A1

公开(公告)日：2024-05-16

申请号：US17986623

申请日：2022-11-14

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ALEXANDRU DUTU ,  NUWAN JAYASENA ,  YASUKO ECKERT ,  NITI MADAN ,  SOORAJ PUTHOOR

IPC: G06F3/06

CPC classification number: G06F3/0625 ,  G06F3/0659 ,  G06F3/0673

Abstract: An apparatus includes a memory controller that includes logic to receive a first memory request having a first request type and a second memory request having a second request type. The apparatus also includes a scheduling unit that includes logic to schedule an order of the first and second memory requests for execution based upon a first parameter value and a second parameter value. The first parameter value corresponds to a utility and energy cost for the first memory request and the second parameter value corresponds to a utility and energy cost for the second memory request.

公开(公告)号：US20220206869A1

公开(公告)日：2022-06-30

申请号：US17135209

申请日：2020-12-28

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： VAIBHAV RAMAKRISHNAN RAMACHANDRAN ,  ALEXANDRU DUTU ,  BRADFORD BECKMANN

IPC: G06F9/50 ,  G06F9/48 ,  G06F9/52 ,  G06F3/06

Abstract: Virtualizing resources of a memory-based execution device is disclosed. A host processing system orchestrates the execution of two or more offload tasks on a remote execution device. The remote execution device includes a memory array coupled to a processing unit that is shared by concurrent processes on the host processing system. The host processing system provides time-multiplexed access to the processing unit by each concurrent process for completing offload tasks on the processing unit. The host processing system initiates a context switch on the remote execution device from a first offload task to a second offload task. The context state of the first offload task is saved on the remote execution device.

公开(公告)号：US20220414013A1

公开(公告)日：2022-12-29

申请号：US17361145

申请日：2021-06-28

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： JOHNATHAN ALSOP ,  ALEXANDRU DUTU ,  SHAIZEEN AGA ,  NUWAN JAYASENA

IPC: G06F12/0871 ,  G06F12/084 ,  G06F12/0846 ,  G06F12/02

Abstract: Dynamically coalescing atomic memory operations for memory-local computing is disclosed. In an embodiment, it is determined whether a first atomic memory access and a second atomic memory access are candidates for coalescing. In response to a triggering event, the atomic memory accesses that are candidates for coalescing are coalesced in a cache prior to requesting memory-local processing by a memory-local compute unit. The atomic memory accesses may be coalesced in the same cache line or atomic memory accesses in different cache lines may be coalesced using a multicast memory-local processing command.