公开(公告)号：US20240045606A1

公开(公告)日：2024-02-08

申请号：US18492081

申请日：2023-10-23

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： JOHNATHAN ALSOP ,  NUWAN JAYASENA ,  SHAIZEEN AGA ,  ANDREW M. MCCRABB

IPC: G06F3/06

CPC classification number: G06F3/064 ,  G06F3/0604 ,  G06F3/0644 ,  G06F3/0659 ,  G06F3/0679

Abstract: Methods and apparatuses to control digital data transfer via a memory channel between a memory module and a processor are disclosed. At least one of the memory module or the processor coalesces a plurality of short data words into multicast coalesced block data comprising a single data block for transfer via the memory channel. Each of the plurality of short data words pertains to one of at least two partitioned memory submodules in the memory module. The multicast coalesced block data is communicated over the memory channel.

公开(公告)号：US20220414013A1

公开(公告)日：2022-12-29

申请号：US17361145

申请日：2021-06-28

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： JOHNATHAN ALSOP ,  ALEXANDRU DUTU ,  SHAIZEEN AGA ,  NUWAN JAYASENA

IPC: G06F12/0871 ,  G06F12/084 ,  G06F12/0846 ,  G06F12/02

Abstract: Dynamically coalescing atomic memory operations for memory-local computing is disclosed. In an embodiment, it is determined whether a first atomic memory access and a second atomic memory access are candidates for coalescing. In response to a triggering event, the atomic memory accesses that are candidates for coalescing are coalesced in a cache prior to requesting memory-local processing by a memory-local compute unit. The atomic memory accesses may be coalesced in the same cache line or atomic memory accesses in different cache lines may be coalesced using a multicast memory-local processing command.

公开(公告)号：US20220027291A1

公开(公告)日：2022-01-27

申请号：US16938364

申请日：2020-07-24

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： SERGEY BLAGODUROV ,  JOHNATHAN ALSOP ,  JAGADISH B. KOTRA ,  MARKO SCRBAK ,  GANESH DASIKA

IPC: G06F13/16 ,  G06F9/30 ,  H04L12/733

Abstract: Arbitrating atomic memory operations, including: receiving, by a media controller, a plurality of atomic memory operations; determining, by an atomics controller associated with the media controller, based on one or more arbitration rules, an ordering for issuing the plurality of atomic memory operations; and issuing the plurality of atomic memory operations to a memory module according to the ordering.

公开(公告)号：US20240168639A1

公开(公告)日：2024-05-23

申请号：US17990092

申请日：2022-11-18

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： SHAIZEEN AGA ,  JOHNATHAN ALSOP ,  NUWAN JAYASENA

IPC: G06F3/06

CPC classification number: G06F3/0613 ,  G06F3/0659 ,  G06F3/0673

Abstract: An apparatus for performing distributed reduction operations using near-memory computation includes memory and a first near-memory compute node. The first-near-memory compute node is coupled to a plurality of near-memory compute nodes. The first near-memory compute node comprises logic to store first data loaded from a second near-memory compute node, perform a reduction operation on the first data and second data to compute a result; and store the result within the first near-memory compute node. In some aspects, the near-memory compute node includes a PIM execution unit and carries out the reduction operation utilizing PIM commands.

公开(公告)号：US20220318085A1

公开(公告)日：2022-10-06

申请号：US17536817

申请日：2021-11-29

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： JOHNATHAN ALSOP ,  SHAIZEEN AGA

IPC: G06F11/07 ,  G06F11/24 ,  G06F11/14

Abstract: Detecting execution hazards in offloaded operations is disclosed. A second offload operation is compared to a first offload operation that precedes the second offload operation. It is determined whether the second offload operation creates an execution hazard on an offload target device based on the comparison of the second offload operation to the first offload operation. If the execution hazard is detected, an error handling operation may be performed. In some examples, the offload operations are processing-in-memory operations.

公开(公告)号：US20220318015A1

公开(公告)日：2022-10-06

申请号：US17218994

申请日：2021-03-31

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： JOHNATHAN ALSOP ,  SHAIZEEN AGA

IPC: G06F9/32 ,  G06F9/38

Abstract: Enforcing data placement requirements via address bit swapping, including: receiving an instruction comprising a first memory address associated with a first address bit mapping; generating a remapped instruction by rearranging a plurality of bits of the first memory address according to a second address bit mapping; and issuing the remapped instruction to memory.