公开(公告)号：US09916246B1

公开(公告)日：2018-03-13

申请号：US15238209

申请日：2016-08-16

Applicant: Advanced Micro Devices, Inc.

Inventor： Carson Donahue Henrion ,  Michael K. Ciraula ,  Gregg Donley ,  Alok Garg ,  Eric Busta

IPC: G06F12/00 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/128

CPC classification number: G06F12/0811 ,  G06F12/0828 ,  G06F12/0833 ,  G06F2212/621 ,  G06F2212/69 ,  G06F2212/70

Abstract: A processing system includes a shadow tag memory, which stores a plurality of entries containing coherency information for the cachelines residing at the various levels of private caches. If a cache miss occurs at a private cache, or if coherency information for a cacheline requires updating, a probe is sent to the shadow tag memory maintained at the shared cache to determine whether the requested (or affected) cacheline is stored at another private cache. The probe includes a tag which can be divided into two or more portions. To more efficiently compare the probe tag to the shadow tag entries, the comparison is performed in multiple stages based on the portions of the probe tag.

公开(公告)号：US11361819B2

公开(公告)日：2022-06-14

申请号：US15841649

申请日：2017-12-14

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Andrew Robison ,  Michael K. Ciraula ,  Eric Busta ,  Carson Donahue Henrion

IPC: G11C11/419 ,  G11C11/418 ,  G11C7/12

Abstract: A processing system reduces by staging precharging of bitlines of a memory. In a static random access memory (SRAM) array, the voltage level on every bitline in the array is precharged to a reference voltage (VDD) rail voltage before a memory access. To facilitate reduction of current spikes from precharging, a precharge control unit groups entries of a RAM into a plurality of subsets, or regions, and applies a different precharge signal for precharging bitlines associated with each subset. Application of the precharge signals to the respective subsets over time results in smaller current spikes than simultaneous application of precharge signals to all of the bitlines.

公开(公告)号：US20180052770A1

公开(公告)日：2018-02-22

申请号：US15238209

申请日：2016-08-16

Applicant: Advanced Micro Devices, Inc.

Inventor： Carson Donahue Henrion ,  Michael K. Ciraula ,  Gregg Donley ,  Alok Garg ,  Eric Busta

IPC: G06F12/0811 ,  G06F12/0815 ,  G06F12/128

CPC classification number: G06F12/0811 ,  G06F12/0828 ,  G06F12/0833 ,  G06F2212/621 ,  G06F2212/69 ,  G06F2212/70

Abstract: A processing system includes a shadow tag memory, which stores a plurality of entries containing coherency information for the cachelines residing at the various levels of private caches. If a cache miss occurs at a private cache, or if coherency information for a cacheline requires updating, a probe is sent to the shadow tag memory maintained at the shared cache to determine whether the requested (or affected) cacheline is stored at another private cache. The probe includes a tag which can be divided into two or more portions. To more efficiently compare the probe tag to the shadow tag entries, the comparison is performed in multiple stages based on the portions of the probe tag.