公开(公告)号：US20200042197A1

公开(公告)日：2020-02-06

申请号：US16052055

申请日：2018-08-01

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Jagadish B. KOTRA ,  Karthik RAO ,  Joseph L. GREATHOUSE

IPC: G06F3/06

Abstract: A system including a stack of two or more layers of volatile memory, such as layers of a 3D stacked DRAM memory, places data in the stack based on a temperature or a refresh rate. When a threshold is exceeded, data are moved from a first region to a second region in the stack, the second region having one or both of a second temperature lower than a first temperature of the first region or a second refresh rate lower than a first refresh rate of the first region.

公开(公告)号：US20210149819A1

公开(公告)日：2021-05-20

申请号：US17135325

申请日：2020-12-28

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Jagadish B. KOTRA ,  Gabriel H. LOH ,  Matthew R. POREMBA

IPC: G06F12/1045 ,  G09C1/00

Abstract: A processing system selectively compresses cache lines at a cache or at a memory or encrypts cache lines at the memory based on evictions of entries mapping virtual-to-physical address translations from a translation lookaside buffer (TLB). Upon eviction of a TLB entry, the processing system identifies cache lines corresponding to the physical addresses of the evicted TLB entry and selectively compresses the cache lines to increase the effective storage capacity of the processing system or encrypts the cache lines to protect against vulnerabilities.

公开(公告)号：US20210182193A1

公开(公告)日：2021-06-17

申请号：US16713940

申请日：2019-12-13

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Weon Taek NA ,  Jagadish B. KOTRA ,  Yasuko ECKERT ,  Steven RAASCH ,  Sergey BLAGODUROV

IPC: G06F12/0811 ,  G06F12/0871 ,  G06F12/0831 ,  G06F12/0882 ,  G06F12/1027 ,  G06F9/30

Abstract: A processing system selectively allocates space to store a group of one or more cache lines at a cache level of a cache hierarchy having a plurality of cache levels based on memory access patterns of a software application executing at the processing system. The processing system generates bit vectors indicating which cache levels are to allocate space to store groups of one or more cache lines based on the memory access patterns, which are derived from data granularity and movement information. Based on the bit vectors, the processing system provides hints to the cache hierarchy indicating the lowest cache level that can exploit the reuse potential for a particular data.

公开(公告)号：US20210034256A1

公开(公告)日：2021-02-04

申请号：US16939814

申请日：2020-07-27

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Jagadish B. KOTRA ,  Karthik RAO ,  Joseph L. GREATHOUSE

IPC: G06F3/06

Abstract: A system including a stack of two or more layers of volatile memory, such as layers of a 3D stacked DRAM memory, places data in the stack based on a temperature or a refresh rate. When a threshold is exceeded, data are moved from a first region to a second region in the stack, the second region having one or both of a second temperature lower than a first temperature of the first region or a second refresh rate lower than a first refresh rate of the first region.