公开(公告)号：US20140177362A1

公开(公告)日：2014-06-26

申请号：US13722716

申请日：2012-12-20

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： James O'CONNOR ,  Warren Kruger

IPC: G11C29/00

CPC classification number: G06F3/0619 ,  G06F3/0659 ,  G06F3/0673 ,  G06F11/1052 ,  G11C7/1006 ,  G11C7/1009 ,  G11C29/76 ,  G11C2029/0411

Abstract: A memory and a method of storing data in a memory are provided. The memory comprises a memory block comprising data bits and additional bits. The memory includes logic which, when receiving a first command, writes data into the data bits of the memory block, wherein the data is masked according to a first input. The logic, in response to a second command, writes data into the data bits of the memory block and writes a second input into the additional bits of the memory block.

Abstract translation: 提供了存储器和将数据存储在存储器中的方法。 存储器包括包括数据位和附加位的存储器块。 存储器包括逻辑，当接收到第一命令时，将数据写入存储器块的数据位，其中根据第一输入对数据进行掩蔽。 响应于第二命令的逻辑将数据写入存储器块的数据位，并将第二个输入写入存储器块的附加位。

公开(公告)号：US20140122801A1

公开(公告)日：2014-05-01

申请号：US13663335

申请日：2012-10-29

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Gabriel LOH ,  James O'CONNOR

IPC: G06F12/14 ,  G06F12/08

CPC classification number: G06F11/3433 ,  G06F11/349 ,  G06F13/1663 ,  G06F2201/86 ,  G06F2201/88

Abstract: Embodiments are described for a method for controlling access to memory in a processor-based system comprising monitoring a number of interference events, such as bank contentions, bus contentions, row-buffer conflicts, and increased write-to-read turnaround time caused by a first core in the processor-based system that causes a delay in access to the memory by a second core in the processor-based system; deriving a control signal based on the number of interference events; and transmitting the control signal to one or more resources of the processor-based system to reduce the number of interference events from an original number of interference events.

Abstract translation: 描述了用于在基于处理器的系统中控制对存储器的访问的方法的实施例，包括监视多个干扰事件，例如银行争用，总线争用，行缓冲器冲突以及由 基于处理器的系统中的第一核心，其导致在基于处理器的系统中由第二核心访问存储器的延迟; 基于干扰事件的数量导出控制信号; 以及将所述控制信号发送到所述基于处理器的系统的一个或多个资源，以从原始数量的干扰事件减少干扰事件的数量。