公开(公告)号：US09851744B2

公开(公告)日：2017-12-26

申请号：US14566265

申请日：2014-12-10

Applicant: Advanced Micro Devices, Inc.

Inventor： Glenn Dearth ,  Anwar Kashem ,  Sean Cummins

IPC: G11C8/00 ,  G06F1/10 ,  G06F13/00 ,  G06F13/16 ,  G11C7/22

CPC classification number: G06F1/10 ,  G06F13/00 ,  G06F13/1689 ,  G11C7/22

Abstract: In one form, an apparatus comprises a delay circuit and a controller. The delay circuit delays a plurality of command and address signals according to a first delay signal and provides a delayed command and address signal to memory interface. The controller performs command and address training in which the controller provides an activation signal and a predetermined address signal with first timing according to the first delay signal, and the plurality of command and address signals besides the predetermined address signal with second timing according to the first delay signal, wherein the second timing is relaxed with respect to the first timing. The controller determines an eye of timing for the predetermined address signal by repetitively providing a predetermined command on the command and address signals, varying the first delay signal, and measuring a data signal received from the memory interface.

公开(公告)号：US20160172013A1

公开(公告)日：2016-06-16

申请号：US14566265

申请日：2014-12-10

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Glenn Dearth ,  Anwar Kashem ,  Sean Cummins

IPC: G11C7/10 ,  G06F1/10

CPC classification number: G06F1/10 ,  G06F13/00 ,  G06F13/1689 ,  G11C7/22

Abstract: In one form, an apparatus comprises a delay circuit and a controller. The delay circuit delays a plurality of command and address signals according to a first delay signal and provides a delayed command and address signal to memory interface. The controller performs command and address training in which the controller provides an activation signal and a predetermined address signal with first timing according to the first delay signal, and the plurality of command and address signals besides the predetermined address signal with second timing according to the first delay signal, wherein the second timing is relaxed with respect to the first timing. The controller determines an eye of timing for the predetermined address signal by repetitively providing a predetermined command on the command and address signals, varying the first delay signal, and measuring a data signal received from the memory interface.

Abstract translation: 在一种形式中，装置包括延迟电路和控制器。 延迟电路根据第一延迟信号延迟多个命令和地址信号，并向存储器接口提供延迟的命令和地址信号。 控制器执行命令和地址训练，其中控制器根据第一延迟信号提供具有第一定时的激活信号和预定地址信号，并且除了具有第二定时的预定地址信号之外的多个命令和地址信号 延迟信号，其中第二定时相对于第一定时被放宽。 控制器通过重复地向命令和地址信号提供预定命令，改变第一延迟信号以及测量从存储器接口接收到的数据信号来确定预定地址信号的定时时间。