公开(公告)号：US20160371211A1

公开(公告)日：2016-12-22

申请号：US14806795

申请日：2015-07-23

Applicant: APPLE INC.

Inventor： Ori Isachar ,  Gil Semo ,  Guy Kushtai ,  Tal Lazmi

IPC: G06F13/40 ,  G06F13/28

CPC classification number: G06F13/4013 ,  G06F13/16 ,  G06F13/287 ,  G06F13/4022

Abstract: An apparatus for use with a memory device that has a plurality of memory-device terminals having respective unique bit significances is described. The apparatus includes a memory controller, which includes (i) a plurality of external terminals, each one of the external terminals configured to be in communication with a respective one of the memory-device terminals, (ii) a plurality of internal terminals having respective unique bit significances, (iii) a switching unit, and (iv) a processor. The processor is configured to drive the memory device to communicate a predetermined sequence of bit patterns to the controller, and, in response to the sequence of bit patterns, drive the switching unit to connect each one of the external terminals to a respective one of the internal terminals having the bit significance of the memory-device terminal with which the external terminal is in communication. Other embodiments are also described.

Abstract translation: 描述了一种与存储器件一起使用的装置，该装置具有多个具有各自独特的比特重要性的存储器件终端。 该装置包括存储器控制器，其包括（i）多个外部端子，每个外部端子被配置为与相应的一个存储器件端子通信，（ii）多个内部端子具有相应的 独特的比特意义，（iii）切换单元，和（iv）处理器。 处理器被配置为驱动存储器设备以将预定的位模式序列传送到控制器，并且响应于位模式的顺序驱动切换单元将每个外部终端连接到相应的一个 内部终端具有与外部终端进行通信的存储器件终端的位有意义。 还描述了其它实施例。

公开(公告)号：US09229525B2

公开(公告)日：2016-01-05

申请号：US13919213

申请日：2013-06-17

Applicant: Apple Inc.

Inventor： Idan Reller ,  Rachel Menes ,  Arie Peled ,  Guy Kushtai

IPC: G06F1/32 ,  G06F13/42

CPC classification number: G06F1/3253 ,  G06F13/161 ,  G06F13/4234 ,  Y02D10/151 ,  Y02D50/20

Abstract: A method includes, in a memory system that includes a host and a storage device connected by a bus interface, assessing in the storage device a power supply state of the memory system. In the storage device a latency tolerance is selected for the bus interface based on the assessed power supply state. The selected latency tolerance is indicated from the storage device to the host, for application to the bus interface.

Abstract translation: 一种方法包括在包括通过总线接口连接的主机和存储设备的存储器系统中，在存储设备中评估存储器系统的电源状态。 在存储设备中，基于评估的电源状态为总线接口选择等待容限。 从存储设备向主机指示所选择的延迟容限，以应用于总线接口。

公开(公告)号：US20140372777A1

公开(公告)日：2014-12-18

申请号：US13919213

申请日：2013-06-17

Applicant: Apple Inc.

Inventor： Idan Reller ,  Rachel Menes ,  Arie Peled ,  Guy Kushtai

IPC: G06F1/32 ,  G06F13/42

CPC classification number: G06F1/3253 ,  G06F13/161 ,  G06F13/4234 ,  Y02D10/151 ,  Y02D50/20

Abstract: A method includes, in a memory system that includes a host and a storage device connected by a bus interface, assessing in the storage device a power supply state of the memory system. In the storage device a latency tolerance is selected for the bus interface based on the assessed power supply state. The selected latency tolerance is indicated from the storage device to the host, for application to the bus interface.

Abstract translation: 一种方法包括在包括通过总线接口连接的主机和存储设备的存储器系统中，在存储设备中评估存储器系统的电源状态。 在存储设备中，基于评估的电源状态为总线接口选择等待容限。 从存储设备向主机指示所选择的延迟容限，以应用于总线接口。