公开(公告)号：US20140215191A1

公开(公告)日：2014-07-31

申请号：US13750972

申请日：2013-01-25

Applicant: APPLE INC.

Inventor： Pradeep Kanapathipillai ,  Hari Kannan ,  Po-Yung Chang ,  Ming-Ta Hsu ,  Rajat Goel

IPC: G06F9/30

CPC classification number: G06F9/30043 ,  G06F9/3834

Abstract: Techniques are disclosed relating to ordering of load instructions in a weakly-ordered memory model. In one embodiment, a processor includes a cache with multiple cache lines and a store queue configured to maintain status information associated with a store instruction that targets a location in one of the cache lines. In this embodiment, the processor is configured to set an indicator in the status information in response to migration of the targeted cache line. The indicator may be usable to sequence performance of load instructions that are younger than the store instruction. For example, the processor may be configured to wait, based on the indicator, to perform a younger load instruction that targets the same location as the store instruction until the store instruction is removed from the store queue. This may prevent forwarding of the value of the store instruction to the younger load and preserve load-load ordering.

Abstract translation: 公开了关于弱有序存储器模型中的加载指令的排序的技术。 在一个实施例中，处理器包括具有多个高速缓存行的高速缓存和存储队列，该存储队列被配置为维护与存储指令相关联的状态信息，所述存储指令针对高速缓存行之一中的位置 在该实施例中，处理器被配置为响应于目标高速缓存线的迁移而将状态信息中的指示符设置成。 该指示符可用于对比小于存储指令的加载指令的性能进行排序。 例如，处理器可以被配置为基于指示符等待执行与存储指令相同的位置的较年轻的加载指令，直到存储指令从存储队列中移除。 这可能会阻止将存储指令的值转发到较小的负载并保持负载负载顺序。

公开(公告)号：US09383995B2

公开(公告)日：2016-07-05

申请号：US13750972

申请日：2013-01-25

Applicant: Apple Inc.

Inventor： Pradeep Kanapathipillai ,  Hari Kannan ,  Po-Yung Chang ,  Ming-Ta Hsu ,  Rajat Goel

IPC: G06F9/30 ,  G06F13/00 ,  G06F9/38

CPC classification number: G06F9/30043 ,  G06F9/3834

Abstract: Techniques are disclosed relating to ordering of load instructions in a weakly-ordered memory model. In one embodiment, a processor includes a cache with multiple cache lines and a store queue configured to maintain status information associated with a store instruction that targets a location in one of the cache lines. In this embodiment, the processor is configured to set an indicator in the status information in response to migration of the targeted cache line. The indicator may be usable to sequence performance of load instructions that are younger than the store instruction. For example, the processor may be configured to wait, based on the indicator, to perform a younger load instruction that targets the same location as the store instruction until the store instruction is removed from the store queue. This may prevent forwarding of the value of the store instruction to the younger load and preserve load-load ordering.

Abstract translation: 公开了关于弱有序存储器模型中的加载指令的排序的技术。 在一个实施例中，处理器包括具有多个高速缓存行的高速缓存和存储队列，该存储队列被配置为维护与存储指令相关联的状态信息，所述存储指令针对高速缓存行之一中的位置 在该实施例中，处理器被配置为响应于目标高速缓存线的迁移而将状态信息中的指示符设置成。 该指示符可用于对比小于存储指令的加载指令的性能进行排序。 例如，处理器可以被配置为基于指示符等待执行与存储指令相同的位置的较年轻的加载指令，直到存储指令从存储队列中移除。 这可能会阻止将存储指令的值转发到较小的负载并保持负载负载顺序。

公开(公告)号：US20130042074A1

公开(公告)日：2013-02-14

申请号：US13651943

申请日：2012-10-15

Applicant: Apple Inc.

Inventor： Sudarshan Kadambi ,  Puneet Kumar ,  Po-Yung Chang

IPC: G06F12/08

CPC classification number: G06F12/0862 ,  G06F9/30047 ,  G06F9/3455 ,  G06F9/383 ,  G06F2212/6028

Abstract: In one embodiment, a processor comprises a prefetch unit coupled to a data cache. The prefetch unit is configured to concurrently maintain a plurality of separate, active prefetch streams. Each prefetch stream is either software initiated via execution by the processor of a dedicated prefetch instruction or hardware initiated via detection of a data cache miss by one or more load/store memory operations. The prefetch unit is further configured to generate prefetch requests responsive to the plurality of prefetch streams to prefetch data in to the data cache.