Partial Perspective Correction with Mitigation of Vertical Disparity

    公开(公告)号:US20240098232A1

    公开(公告)日:2024-03-21

    申请号:US18369621

    申请日:2023-09-18

    Applicant: Apple Inc.

    CPC classification number: H04N13/117 H04N13/383

    Abstract: In one implementation, a method of performing perspective correction is performed by a device having a three-dimensional device coordinate system and including a first image sensor, a first display, one or more processors, and non-transitory memory. The method includes capturing, using the first image sensor, a first image of a physical environment. The method includes transforming the first image from a first perspective of the first image sensor to a second perspective based on a difference between the first perspective and the second perspective, wherein the second perspective is a first distance away from a location corresponding to a first eye of a user less than a second distance between the first perspective and the location corresponding to the first eye of the user. The method includes displaying, on the first display, the transformed first image of the physical environment.

    I-FRAME FLASHING FIX IN VIDEO ENCODING AND DECODING
    3.
    发明申请
    I-FRAME FLASHING FIX IN VIDEO ENCODING AND DECODING 审中-公开
    I-FRAME闪光灯在视频编码和解码中

    公开(公告)号:US20150350688A1

    公开(公告)日:2015-12-03

    申请号:US14696032

    申请日:2015-04-24

    Applicant: Apple Inc.

    CPC classification number: H04N19/103 H04N19/154

    Abstract: Methods and systems provide video compression to reduce a “flashing” effect, typically caused by skipping coding or allocating a low number of bits in coding relatively low complexity portions of frames. In an embodiment, if at least a portion of a sequence of frames is of relatively low complexity, a history of coding blocks may be considered to determine whether to skip coding. In an embodiment, a number of coding bits allocated to a block may be increased based on a history of the coding block and a likelihood of flashing. The history of coding of each pixel block may be a basis for forcing a higher quantization parameter coding of pixel block(s) of high motion portions such that a low bit rate is maintained despite a larger number of bits being allocated to flashing-susceptible blocks. In another embodiment, force coding of relatively low complexity portions may be delayed by a number of frames.

    Abstract translation: 方法和系统提供视频压缩以减少“闪烁”效应,通常是由于在编码相对低复杂度的帧部分中编码或分配低数量的比特来引起的。 在一个实施例中,如果帧序列的至少一部分具有相对低的复杂度,则可以考虑编码块的历史以确定是否跳过编码。 在一个实施例中,可以基于编码块的历史和闪烁的可能性来增加分配给块的编码比特数。 每个像素块的编码历史可以是用于强制高运动部分的像素块的较高量化参数编码的基础,使得尽管将较大数量的比特分配给闪烁敏感块,维持低比特率 。 在另一个实施例中,相对低复杂度部分的强制编码可能被延迟多个帧。

    Compiling models for dedicated hardware

    公开(公告)号:US11468338B2

    公开(公告)日:2022-10-11

    申请号:US16262809

    申请日:2019-01-30

    Applicant: Apple Inc.

    Abstract: The subject technology provides receiving a neural network (NN) model to be executed on a target platform, the NN model including multiple layers that include operations and some of the operations being executable on multiple processors of the target platform. The subject technology further sorts the operations from the multiple layers in a particular order based at least in part on grouping the operations that are executable by a particular processor of the multiple processors. The subject technology determines, based at least in part on a cost of transferring the operations between the multiple processors, an assignment of one of the multiple processors for each of the sorted operations of each of the layers in a manner that minimizes a total cost of executing the operations. Further, for each layer of the NN model, the subject technology includes an annotation to indicate the processor assigned for each of the operations.

    HYPOTHETICAL REFERENCE DECODER
    6.
    发明申请
    HYPOTHETICAL REFERENCE DECODER 审中-公开
    假想参考解码器

    公开(公告)号:US20140153653A1

    公开(公告)日:2014-06-05

    申请号:US14175555

    申请日:2014-02-07

    Applicant: APPLE INC.

    CPC classification number: H04N19/44 H04N19/149 H04N19/152

    Abstract: Disclosed is a system and method of controlling a video decoder, including a reviewing channel data representing coded video data generated by an encoder to identify parameters of a hypothetical reference decoder (HRD) used by the encoder during coding operations. A parameter representing an exit data rate requirement of a coded picture buffer (CPB) of the HRD is compared against exit rate performance of the video decoder. If the exit rate performance of the video coder matches the exit rate requirement of the HRD, the coded video data is decoded, otherwise, a certain decoding degradation scheme can be applied, including disabling decoder from decoding the coded video data.

    Abstract translation: 公开了一种控制视频解码器的系统和方法,包括:代表由编码器产生的编码视频数据的查看频道数据,以识别由编码器在编码操作期间使用的假设参考解码器(HRD)的参数。 将表示HRD的编码图像缓冲器(CPB)的退出数据速率要求的参数与视频解码器的退出速率性能进行比较。 如果视频编码器的退出速率性能与HRD的退出率要求相匹配,则编码的视频数据被解码,否则可以应用某种解码劣化方案,包括禁止解码器解码编码的视频数据。

    Compiling models for dedicated hardware

    公开(公告)号:US12175375B2

    公开(公告)日:2024-12-24

    申请号:US17903991

    申请日:2022-09-06

    Applicant: Apple Inc.

    Abstract: The subject technology provides receiving a neural network (NN) model to be executed on a target platform, the NN model including multiple layers that include operations and some of the operations being executable on multiple processors of the target platform. The subject technology further sorts the operations from the multiple layers in a particular order based at least in part on grouping the operations that are executable by a particular processor of the multiple processors. The subject technology determines, based at least in part on a cost of transferring the operations between the multiple processors, an assignment of one of the multiple processors for each of the sorted operations of each of the layers in a manner that minimizes a total cost of executing the operations. Further, for each layer of the NN model, the subject technology includes an annotation to indicate the processor assigned for each of the operations.

    Enhanced image processing techniques for deep neural networks

    公开(公告)号:US11367163B2

    公开(公告)日:2022-06-21

    申请号:US16794824

    申请日:2020-02-19

    Applicant: Apple Inc.

    Abstract: Artistic styles extracted from source images may be applied to target images to generate stylized images and/or video sequences. The extracted artistic styles may be stored as a plurality of layers in one or more neural networks, which neural networks may be further optimized, e.g., via the fusion of various elements of the networks' architectures. The artistic style may be applied to the target images and/or video sequences using various optimization methods, such as the use of a first version of the neural network by a first processing device at a first resolution to generate one or more sets of parameters (e.g., scaling and/or biasing parameters), which parameters may then be mapped for use by a second version of the neural network by a second processing device at a second resolution. Analogous multi-processing device and/or multi-network solutions may also be applied to other complex image processing tasks for increased efficiency.

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