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公开(公告)号：US12277420B2
公开(公告)日：2025-04-15
申请号：US18247595
申请日：2021-08-17
Applicant: ARM LIMITED
Inventor： Jacob Eapen , Matthias Lothar Boettcher , Balaji Venu , François Christopher Jacques Botman
IPC: G06F9/30
Abstract: A masked-vector-comparison instruction specifies a source vector operand comprising a plurality of source data elements, a mask value, and a comparison target operand. In response to the masked-vector-comparison instruction, an instruction decoder 10 controls processing circuitry 16 to: for each active source data element of the source vector operand, determine whether the active source data element satisfies a comparison condition, based on a masked comparison between one or more compared bits of the active source data element and one or more compared bits of the comparison target operand, the mask value specifying a pattern of compared bits and non-compared bits within the comparison target operand and the active source data element; and generate a result value indicative of which of the source data elements of the source vector operand, if any, is an active source data element satisfying the comparison condition. This instruction is useful for variable length decoding operations.
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公开(公告)号：US20240202139A1
公开(公告)日：2024-06-20
申请号：US18556477
申请日：2022-02-17
Applicant: Arm Limited
CPC classification number: G06F12/1458 , G06F21/604
Abstract: There is provided an apparatus, method and computer program for constraining memory accesses. The apparatus comprises processing circuitry to perform operations during which access requests to memory are generated. The processing circuitry is arranged to generate memory addresses for the access requests using capabilities that identify constraining information. The apparatus further comprises capability checking circuitry to perform a capability check operation to determine whether a given access request whose memory address is generated using a given capability is permitted based on given constraining information identified by the given capability. The capability check operation includes performing a range check based on range constraining information provided by the given constraining information, and when a determined condition is met, to perform the range check in dependence on both the range constraining information and an item of state information of the apparatus which varies dynamically during performance of the operations of the processing circuitry.
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公开(公告)号：US11720619B2
公开(公告)日：2023-08-08
申请号：US17098815
申请日：2020-11-16
Applicant: Arm Limited
IPC: G06F16/35 , G06F16/33 , G06F16/335
CPC classification number: G06F16/355 , G06F16/335
Abstract: Data processing apparatuses, methods and computer programs are disclosed. A range definition register is arranged to store a range specifier and filtering operations are performed with respect to a specified transaction by reference to the range definition register. The range definition register stores the range specifier in a format comprising a significand and an exponent, wherein a range of data identifiers is at least partially defined by the range specifier. When the specified transaction is with respect to a data identifier within the range of data identifiers, the filtering operations performed are dependent on attribute data associated with the range of data identifiers.
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公开(公告)号：US12056062B2
公开(公告)日：2024-08-06
申请号：US17759973
申请日：2020-12-02
Applicant: ARM LIMITED
CPC classification number: G06F12/1458 , G06F9/3005 , G06F9/35
Abstract: Apparatus comprises a processor to execute program instructions stored at respective memory addresses, processing of the program instructions being constrained by a prevailing capability defining at least access permissions to a set of one or more memory addresses; the processor comprising: control flow change handling circuitry to perform a control flow change operation, the control flow change operation defining a control flow change target address indicating the address of a program instruction for execution after the control flow change operation; and capability generating circuitry to determine, in dependence on the control flow change target address, an address at which capability access permissions data is stored; the capability generating circuitry being configured to retrieve the capability access permissions data and to generate a capability for use as a next prevailing capability in dependence upon at least the capability access permissions data.
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公开(公告)号：US20240193101A1
公开(公告)日：2024-06-13
申请号：US18556468
申请日：2022-02-17
Applicant: Arm Limited
IPC: G06F12/14
CPC classification number: G06F12/1458
Abstract: A technique is provided for constraining access to memory using capabilities. An apparatus is provided that has processing circuitry for performing operations during which access request to memory are generated, wherein the processing circuitry is arranged to generate memory addresses for the access requests using capabilities that provide a pointer value and associated constraining information. The apparatus also provides capability generation circuitry, that is responsive to the processing circuitry executing a capability generating instruction that identifies a location in a literal pool of the memory, to retrieve a literal value from the location in the literal pool, and to produce a generated capability in which the pointer value of the generated capability is determined from the literal value. The constraining information of the generated capability is selected from a limited set of options in dependence on information specified by the capability generating instruction. It has been found that such an approach provides a robust mechanism for generating capabilities, whilst reducing code size.
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Patent Agency Ranking
公开(公告)号：US11561882B2
公开(公告)日：2023-01-24
申请号：US16332130
申请日：2017-08-09
Applicant: ARM LIMITED
Inventor： François Christopher Jacques Botman , Thomas Christopher Grocutt , John Michael Horley , Michael John Williams , Michael John Gibbs
Abstract: An apparatus and method are provided for generating and processing a trace stream indicative of instruction execution by processing circuitry. An apparatus has an input interface for receiving instruction execution information from the processing circuitry indicative of a sequence of instructions executed by the processing circuitry, and trace generation circuitry for generating from the instruction execution information a trace stream comprising a plurality of trace elements indicative of execution by the processing circuitry of instruction flow changing instructions within the sequence. The sequence may include a branch behaviour setting instruction that indicates an identified instruction within the sequence, where execution of the branch behaviour setting instruction enables a branch behaviour to be associated with the identified instruction that causes the processing circuitry to branch to a target address identified by the branch behaviour setting instruction when the identified instruction is encountered in the sequence. The trace generation circuitry is further arranged to generate, from the instruction execution information, a trace element indicative of execution behaviour of the branch behaviour setting instruction, and a trace element to indicate that the branch behaviour has been triggered on encountering the identified instruction within the sequence. This enables a very efficient form of trace stream to be used even in situations where the instruction sequence executed by the processing circuitry includes such branch behaviour setting instructions.
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7.发明授权公开(公告)号：US11294787B2
公开(公告)日：2022-04-05
申请号：US16321503
申请日：2017-08-10
Applicant: ARM LIMITED
Inventor： François Christopher Jacques Botman , Thomas Christopher Grocutt , John Michael Horley , Michael John Williams
Abstract: An apparatus and method are provided to control assertion of a trigger signal to processing circuitry. The apparatus has evaluation circuitry to receive program instruction execution information indicative of a program instruction executed by the processing circuitry, which is arranged to perform an evaluation operation to determine with reference to evaluation information whether the program instruction execution information indicates presence of a trigger condition. Trigger signal generation circuitry is used to assert a trigger signal to the processing circuitry in dependence on whether the trigger condition is determined to be present. Further, filter circuitry is arranged to receive event information indicative of at least one event occurring within the processing circuitry, and is arranged to determine with reference to filter control information and that event information whether a qualifying condition is present. The filter circuitry is arranged, on determining that the qualifying condition is not present, to prevent the presence of the trigger condition being notified to the trigger signal generation circuitry. This allows the monitoring of particular program instruction execution behaviour to be qualified so that the processing circuitry is only notified if in addition a qualifying event is determined to be present.
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公开(公告)号：US20240411935A1
公开(公告)日：2024-12-12
申请号：US18700886
申请日：2022-09-14
Applicant: Arm Limited
IPC: G06F21/64
Abstract: An apparatus and method are described for handling sealed capabilities. The apparatus has processing circuitry to perform processing operations during which access requests to memory are generated, wherein the processing circuitry is arranged to generate memory addresses for the access requests using capabilities that identify constraining information. Checking circuitry then determines whether a given access request whose memory address is generated using a given capability is permitted based on the constraining information identified by that given capability, and based on a level of trust associated with the given access request. Each capability has a capability level of trust associated therewith, and the level of trust associated with the given access request is dependent on both a current mode level of trust associated with a current mode of operation of the processing circuitry, and the capability level of trust of the given capability. At least one of the capabilities is settable as a sealed capability, and the apparatus further comprises sealed capability handling circuitry to prevent the processing circuitry performing at least one processing operation using a given sealed capability when the current mode level of trust is a lower level of trust than the capability level of trust of the given sealed capability.
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公开(公告)号：US11086715B2
公开(公告)日：2021-08-10
申请号：US16251503
申请日：2019-01-18
Applicant: Arm Limited
Abstract: An apparatus comprising data processing circuitry for processing data in one of a plurality of operating states, an instruction decoder for decoding instructions and error checking circuitry for performing error checking operations. In response to a touch instruction being decoded by the instruction decoder, error checking operation is performed on selected architectural state. The architectural state is architecturally inaccessible to the operating state. As a result of the touch instruction, the architectural state remains unchanged, at least when no error is detected.
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公开(公告)号：US10303399B2
公开(公告)日：2019-05-28
申请号：US15834434
申请日：2017-12-07
Applicant: ARM LIMITED
Abstract: An apparatus and method are provided for controlling vector memory accesses. The apparatus comprises a set of vector registers, and flag setting circuitry that is 5 responsive to a determination that a vector generated for storage in one of the vector registers comprises a plurality of elements that meet specified contiguousness criteria, to generate flag information associated with that vector register. Processing circuitry is then used to perform a vector memory access operation in order to access in memory a plurality of data values at addresses determined from an address vector operand 10 comprising a plurality of address elements. The address vector operand is provided in a specified vector register of the vector register set, such that the plurality of elements of the vector stored in that specified vector register form the plurality of address elements. The processing circuitry is arranged to determine whether the specified vector register has flag information associated therewith, and if it does, then that flag information is 15 used when determining a number of accesses to memory required to access the plurality of data values. This provides an efficient mechanism for allowing gather or scatter type memory access operations to be implemented using a reduced number of accesses to memory in certain situations where the flag information has been generated for the associated address vector operand.
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