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公开(公告)号：US09823298B2
公开(公告)日：2017-11-21
申请号：US14824093
申请日：2015-08-12
Applicant: ARM Limited
Inventor： Satheesh Balasubramanian , Shardendu Shekhar , James Dennis Dodrill , Sainarayanan Karatholuvu Suryanarayanan
CPC classification number: G01R31/2882 , G01R31/31725 , G06F17/5031 , G06F17/5036 , G06F17/505 , G06F17/5072 , G06F17/5081 , G06F2217/82 , G06F2217/84
Abstract: Various implementations described herein are directed to a system and methods for implementing a critical path architect. In one implementation, the critical path architect may be implemented with a system having a processor and memory including instructions stored thereon that, when executed by the processor, cause the processor to analyze timing data of an integrated circuit. The timing data may include transition times for cells along paths of the integrated circuit. The instructions may cause the processor to identify instances of timing degradation for the cells along the paths of the integrated circuit. The instructions may cause the processor to recommend changes for the instances of the cells along the paths having timing degradation.
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公开(公告)号：US20180074116A1
公开(公告)日：2018-03-15
申请号：US15817643
申请日：2017-11-20
Applicant: ARM Limited
Inventor： Satheesh Balasubramanian , Shardendu Shekhar , James Dennis Dodrill , Sainarayanan Karatholuvu Suryanarayanan
CPC classification number: G01R31/2882 , G01R31/31725 , G06F17/5031 , G06F17/5036 , G06F17/505 , G06F17/5072 , G06F17/5081 , G06F2217/82 , G06F2217/84
Abstract: Various implementations described herein are directed to a system and methods for implementing a critical path architect. In one implementation, the critical path architect may be implemented with a system having a processor and memory including instructions stored thereon that, when executed by the processor, cause the processor to analyze timing data of an integrated circuit. The timing data may include transition times for cells along paths of the integrated circuit. The instructions may cause the processor to identify instances of timing degradation for the cells along the paths of the integrated circuit. The instructions may cause the processor to recommend changes for the instances of the cells along the paths having timing degradation.
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公开(公告)号：US20170045576A1
公开(公告)日：2017-02-16
申请号：US14824093
申请日：2015-08-12
Applicant: ARM Limited
Inventor： Satheesh Balasubramanian , Shardendu Shekhar , James Dennis Dodrill , Sainarayanan Karatholuvu Suryanarayanan
CPC classification number: G01R31/2882 , G01R31/31725 , G06F17/5031 , G06F17/5036 , G06F17/505 , G06F17/5072 , G06F17/5081 , G06F2217/82 , G06F2217/84
Abstract: Various implementations described herein are directed to a system and methods for implementing a critical path architect. In one implementation, the critical path architect may be implemented with a system having a processor and memory including instructions stored thereon that, when executed by the processor, cause the processor to analyze timing data of an integrated circuit. The timing data may include transition times for cells along paths of the integrated circuit. The instructions may cause the processor to identify instances of timing degradation for the cells along the paths of the integrated circuit. The instructions may cause the processor to recommend changes for the instances of the cells along the paths having timing degradation.
Abstract translation: 本文所描述的各种实现涉及用于实现关键路径建筑师的系统和方法。 在一个实现中，关键路径架构师可以利用具有处理器和存储器的系统来实现，所述处理器和存储器包括存储在其上的指令，当由处理器执行时，处理器和存储器使处理器分析集成电路的定时数据。 定时数据可以包括沿着集成电路的路径的小区的转换时间。 指令可能导致处理器识别沿着集成电路的路径的单元的定时劣化的实例。 这些指令可能导致处理器推荐沿着具有定时劣化的路径的单元的实例的改变。
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