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Patent Agency Ranking
公开(公告)号：US09823298B2
公开(公告)日：2017-11-21
申请号：US14824093
申请日：2015-08-12
Applicant: ARM Limited
Inventor： Satheesh Balasubramanian , Shardendu Shekhar , James Dennis Dodrill , Sainarayanan Karatholuvu Suryanarayanan
CPC classification number: G01R31/2882 , G01R31/31725 , G06F17/5031 , G06F17/5036 , G06F17/505 , G06F17/5072 , G06F17/5081 , G06F2217/82 , G06F2217/84
Abstract: Various implementations described herein are directed to a system and methods for implementing a critical path architect. In one implementation, the critical path architect may be implemented with a system having a processor and memory including instructions stored thereon that, when executed by the processor, cause the processor to analyze timing data of an integrated circuit. The timing data may include transition times for cells along paths of the integrated circuit. The instructions may cause the processor to identify instances of timing degradation for the cells along the paths of the integrated circuit. The instructions may cause the processor to recommend changes for the instances of the cells along the paths having timing degradation.
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公开(公告)号：US20190392103A1
公开(公告)日：2019-12-26
申请号：US16013937
申请日：2018-06-21
Applicant: Arm Limited
IPC: G06F17/50
Abstract: Various implementations described herein are directed to a system and methods for validating data points associated with an integrated circuit. In one implementation, the method may include retrieving data table associated with an integrated circuit, wherein the data table includes characterized electrical data associated with one or more cells of the integrated circuit. Further, the method may include converting the data table to one or more relative matrices. The one or more relative matrices are analyzed to determine a trend formed by entries of the one or more relative matrices. Further, the method may include determining whether one or more entries of the one or more relative matrices deviate from the trend. In response to the determination, the data table is flagged.
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公开(公告)号：US20180074116A1
公开(公告)日：2018-03-15
申请号：US15817643
申请日：2017-11-20
Applicant: ARM Limited
Inventor： Satheesh Balasubramanian , Shardendu Shekhar , James Dennis Dodrill , Sainarayanan Karatholuvu Suryanarayanan
CPC classification number: G01R31/2882 , G01R31/31725 , G06F17/5031 , G06F17/5036 , G06F17/505 , G06F17/5072 , G06F17/5081 , G06F2217/82 , G06F2217/84
Abstract: Various implementations described herein are directed to a system and methods for implementing a critical path architect. In one implementation, the critical path architect may be implemented with a system having a processor and memory including instructions stored thereon that, when executed by the processor, cause the processor to analyze timing data of an integrated circuit. The timing data may include transition times for cells along paths of the integrated circuit. The instructions may cause the processor to identify instances of timing degradation for the cells along the paths of the integrated circuit. The instructions may cause the processor to recommend changes for the instances of the cells along the paths having timing degradation.
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公开(公告)号：US20170045576A1
公开(公告)日：2017-02-16
申请号：US14824093
申请日：2015-08-12
Applicant: ARM Limited
Inventor： Satheesh Balasubramanian , Shardendu Shekhar , James Dennis Dodrill , Sainarayanan Karatholuvu Suryanarayanan
CPC classification number: G01R31/2882 , G01R31/31725 , G06F17/5031 , G06F17/5036 , G06F17/505 , G06F17/5072 , G06F17/5081 , G06F2217/82 , G06F2217/84
Abstract: Various implementations described herein are directed to a system and methods for implementing a critical path architect. In one implementation, the critical path architect may be implemented with a system having a processor and memory including instructions stored thereon that, when executed by the processor, cause the processor to analyze timing data of an integrated circuit. The timing data may include transition times for cells along paths of the integrated circuit. The instructions may cause the processor to identify instances of timing degradation for the cells along the paths of the integrated circuit. The instructions may cause the processor to recommend changes for the instances of the cells along the paths having timing degradation.
Abstract translation: 本文所描述的各种实现涉及用于实现关键路径建筑师的系统和方法。 在一个实现中，关键路径架构师可以利用具有处理器和存储器的系统来实现，所述处理器和存储器包括存储在其上的指令，当由处理器执行时，处理器和存储器使处理器分析集成电路的定时数据。 定时数据可以包括沿着集成电路的路径的小区的转换时间。 指令可能导致处理器识别沿着集成电路的路径的单元的定时劣化的实例。 这些指令可能导致处理器推荐沿着具有定时劣化的路径的单元的实例的改变。
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公开(公告)号：US09479147B2
公开(公告)日：2016-10-25
申请号：US14531419
申请日：2014-11-03
Applicant: ARM LIMITED
Inventor： Satheesh Balasubramanian , James Dennis Dodrill
IPC: H03K3/356 , H03K3/3562 , H03K3/037
CPC classification number: H03K3/35625 , H03K3/0372
Abstract: A synchronizer flip-flop is provided, which is able to better respond to input values that are not provided for the necessary setup or hold times. The flip-flop includes a latch that includes inverter circuitry for producing a first signal and a signal in dependence on a value of an input signal at a node. A clocked inverter includes a first switch that is connected between a first reference voltage supply and an intermediate node and a second switch, which is connected between the intermediate node and a second reference voltage supply. The first switch is controlled by the first signal and the second switch is controlled by the second signal to produce an output signal at the intermediate node.
Abstract translation: 提供了同步器触发器，其能够更好地响应不为必要的建立或保持时间提供的输入值。 触发器包括锁存器，其包括用于根据节点处的输入信号的值产生第一信号和信号的反相器电路。 时钟反相器包括连接在第一参考电压源和中间节点之间的第一开关和连接在中间节点和第二参考电压源之间的第二开关。 第一开关由第一信号控制，第二开关由第二信号控制，以在中间节点产生输出信号。
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