公开(公告)号：US20230377676A1

公开(公告)日：2023-11-23

申请号：US17883607

申请日：2022-08-09

Applicant: ASPEED Technology Inc.

Inventor： Hung-Ming Lin ,  Hung-Ju Huang

IPC: G11C29/52 ,  G11C29/02 ,  G11C7/10 ,  G06F7/58

CPC classification number: G11C29/52 ,  G11C29/022 ,  G11C7/1039 ,  G06F7/58

Abstract: The disclosure provides an integrated circuit and an operation method and an inspection method thereof. The integrated circuit includes a one-time programmable (OTP) memory, an identifier generation circuit, and a memory controller. The identifier generation circuit generates a random number, and performs an error-detection-code encoding operation on the random number to generate an identifier with an error-detection code. The memory controller writes the identifier generated by the identifier generation circuit into the OTP memory. The identifier generation circuit reads the identifier from the OTP memory through the memory controller, and performs an error-detection-code decoding operation on the identifier provided by the memory controller to determine whether an error of the identifier from the OTP memory is correctable. When it is determined that the error of the identifier from the OTP memory is not correctable, the writing of the identifier is deemed failed.

公开(公告)号：US08698531B1

公开(公告)日：2014-04-15

申请号：US13759939

申请日：2013-02-05

Applicant: Aspeed Technology Inc.

Inventor： Fu-Chou Hsu ,  Hung-Ju Huang ,  Chung-Yen Lu

IPC: H03K3/02

CPC classification number: G06F15/177

Abstract: An integrated circuit with automatic configuration is disclosed. The integrated circuit comprises a plurality of controllers and a clock detection device. The controllers share a plurality of common pins. The clock detection device coupled to a specified common pin for performing clock detection operations on an external clock signal through the specified common pin according to a plurality of predetermined thresholds and generating a plurality of control signals to the controllers so that only one controller is enabled and performs signal transmission through the common pins.

Abstract translation: 公开了具有自动配置的集成电路。 集成电路包括多个控制器和时钟检测装置。 控制器共享多个公共引脚。 时钟检测装置耦合到指定的公共引脚，用于根据多个预定阈值通过指定的公共引脚对外部时钟信号执行时钟检测操作，并向控制器生成多个控制信号，使得只有一个控制器被使能， 通过公共引脚进行信号传输。

公开(公告)号：US09558086B2

公开(公告)日：2017-01-31

申请号：US14728557

申请日：2015-06-02

Applicant: ASPEED Technology Inc.

Inventor： Hung-Ju Huang ,  Fu-Chou Hsu ,  Chung-Yen Lu

IPC: G06F11/00 ,  G06F11/22 ,  G06F13/42

CPC classification number: G06F11/221 ,  G06F11/2205 ,  G06F11/27 ,  G06F13/4282

Abstract: A System on Chip (SOC) is disclosed. The SOC comprises a first UART controller, a second UART controller, a debug controller, a processor, a UART port, a first multiplexer and a second multiplexer. The first UART controller and the second UART controller have different baud rates. The UART port has a R×D pin coupled to a R×D pin of the second UART controller. The debug controller generates a control signal with a first state and checks whether a received data from the UART controller is equal to a keyword after power-up or a hardware reset. When the received data from the second UART controller is equal to the keyword, the debug controller generates the control signal with the second state, and starts parsing and executing at least one debug command from the second UART controller.

Abstract translation: 公开了片上系统（SOC）。 该SOC包括第一UART控制器，第二UART控制器，调试控制器，处理器，UART端口，第一多路复用器和第二多路复用器。 第一个UART控制器和第二个UART控制器具有不同的波特率。 UART端口的R×D引脚与第二个UART控制器的R×D引脚相连。 调试控制器产生具有第一状态的控制信号，并检查在上电或硬件复位后，来自UART控制器的接收数据是否等于关键字。 当来自第二UART控制器的接收数据等于关键字时，调试控制器产生具有第二状态的控制信号，并且从第二UART控制器开始解析和执行至少一个调试命令。

公开(公告)号：US12119073B2

公开(公告)日：2024-10-15

申请号：US17883607

申请日：2022-08-09

Applicant: ASPEED Technology Inc.

Inventor： Hung-Ming Lin ,  Hung-Ju Huang

IPC: G11C29/52 ,  G06F7/58 ,  G11C7/10 ,  G11C29/02

CPC classification number: G11C29/52 ,  G06F7/58 ,  G11C7/1039 ,  G11C29/022

Abstract: The disclosure provides an integrated circuit and an operation method and an inspection method thereof. The integrated circuit includes a one-time programmable (OTP) memory, an identifier generation circuit, and a memory controller. The identifier generation circuit generates a random number, and performs an error-detection-code encoding operation on the random number to generate an identifier with an error-detection code. The memory controller writes the identifier generated by the identifier generation circuit into the OTP memory. The identifier generation circuit reads the identifier from the OTP memory through the memory controller, and performs an error-detection-code decoding operation on the identifier provided by the memory controller to determine whether an error of the identifier from the OTP memory is correctable. When it is determined that the error of the identifier from the OTP memory is not correctable, the writing of the identifier is deemed failed.