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    Method and apparatus for generating panoramic image with stitching process
    2.
    发明授权
    Method and apparatus for generating panoramic image with stitching process 有权

    公开(公告)号：US10104288B2

    公开(公告)日：2018-10-16

    申请号：US15427504

    申请日：2017-02-08

    Applicant: ASPEED Technology Inc.

    Inventor： Pei-Hen Hung ,  Chung-Yen Lu ,  Kuo-Wei Yeh ,  Jing-Chuan Chen

    IPC: H04N5/232 ,  G06T3/40 ,  G06T3/00 ,  G06T11/60

    Abstract: A vertex processing device applied in an image processing system having an image capture module is disclosed. The image capture module generates camera images. The vertex processing device comprises a coefficient interpolation unit and a coordinate modifying unit. The coefficient interpolation unit generates an interpolated warping coefficient for each camera image with respect to each vertex from a vertex list based on n number of warping coefficients and its original texture coordinates in each camera image. The coordinate modifying unit calculates modified texture coordinates in each camera image for each vertex according to the interpolated warping coefficient and its original texture coordinates in each camera image. The vertex list comprises vertices with data structures that define vertex mapping between the camera images and a panoramic image. The n number of warping coefficients correspond to n number of overlap regions in the panoramic image.

    Apparatus and method for combining video frame and graphics frame
    3.
    发明授权
    Apparatus and method for combining video frame and graphics frame 有权
    用于组合视频帧和图形帧的装置和方法

    公开(公告)号：US09466089B2

    公开(公告)日：2016-10-11

    申请号：US14508851

    申请日：2014-10-07

    Applicant: ASPEED TECHNOLOGY INC.

    Inventor： Chung-Yen Lu

    IPC: G09G5/00 ,  G06T1/20 ,  H04N19/85

    CPC classification number: G06T1/20 ,  G06F3/14 ,  G09G5/00 ,  G09G2350/00 ,  G09G2370/022 ,  H04N19/85

    Abstract: A signal processor of the invention includes a host processor, a command queue, a graphics decoding circuit, a video decoding circuit, a composition engine and two display buffers. The host processor generates graphics commands and sets a video flag to active based on graphics encoded data, video encoded data and mask encoded data from a network. The command queue asserts a control signal according to the graphics commands. The graphics decoding circuit generates the graphics frame and two surface mask while the video decoding circuit generates the video frame and a video mask. The composition engine transfers the graphics frame, the video frame or a content of one of two display buffers to the other display buffer according to the video mask and the two surface masks when the control signal is asserted or when the video flag is active.

    Abstract translation: 本发明的信号处理器包括主处理器，命令队列，图形解码电路，视频解码电路，组合引擎和两个显示缓冲器。 主机处理器根据图形编码数据，视频编码数据和来自网络的掩码编码数据，生成图形命令并将视频标志设置为有效。 命令队列根据图形命令声明控制信号。 图形解码电路在视频解码电路产生视频帧和视频掩码的同时产生图形帧和两个表面掩码。 组合引擎在控制信号被断言时或当视频标志有效时，根据视频掩码和两个表面掩模将图形帧，视频帧或两个显示缓冲器之一的内容传送到另一显示缓冲器。

    Integrated circuit with automatic configuration and method thereof
    4.
    发明授权
    Integrated circuit with automatic configuration and method thereof 有权
    具有自动配置的集成电路及其方法

    公开(公告)号：US08698531B1

    公开(公告)日：2014-04-15

    申请号：US13759939

    申请日：2013-02-05

    Applicant: Aspeed Technology Inc.

    Inventor： Fu-Chou Hsu ,  Hung-Ju Huang ,  Chung-Yen Lu

    IPC: H03K3/02

    CPC classification number: G06F15/177

    Abstract: An integrated circuit with automatic configuration is disclosed. The integrated circuit comprises a plurality of controllers and a clock detection device. The controllers share a plurality of common pins. The clock detection device coupled to a specified common pin for performing clock detection operations on an external clock signal through the specified common pin according to a plurality of predetermined thresholds and generating a plurality of control signals to the controllers so that only one controller is enabled and performs signal transmission through the common pins.

    Abstract translation: 公开了具有自动配置的集成电路。 集成电路包括多个控制器和时钟检测装置。 控制器共享多个公共引脚。 时钟检测装置耦合到指定的公共引脚，用于根据多个预定阈值通过指定的公共引脚对外部时钟信号执行时钟检测操作，并向控制器生成多个控制信号，使得只有一个控制器被使能， 通过公共引脚进行信号传输。

    Variable length coding and decoding methods and devices for grouped pixels
    5.
    发明授权
    Variable length coding and decoding methods and devices for grouped pixels 有权

    公开(公告)号：US10110931B2

    公开(公告)日：2018-10-23

    申请号：US15140085

    申请日：2016-04-27

    Applicant: ASPEED Technology Inc.

    Inventor： Chung-Yen Lu

    IPC: H04N19/91 ,  H04N19/147 ,  H04N19/13 ,  H04N19/18 ,  H04N19/182

    Abstract: A variable length coder is disclosed. The variable length coder comprises a size determining unit and a first residual coder. The size determining unit determines a maximum size based on sizes of quantized residuals in a current group and determines whether to enable the first residual coder according to the maximum size. When the maximum size is equal to 1, the first residual coder is enabled to encode the quantized residuals as one symbol to generate a first encoded suffix according to a variable length coding scheme.

    System on chip with debug controller and operating method thereof
    7.
    发明授权
    System on chip with debug controller and operating method thereof 有权
    具有调试控制器的片上系统及其操作方法

    公开(公告)号：US09558086B2

    公开(公告)日：2017-01-31

    申请号：US14728557

    申请日：2015-06-02

    Applicant: ASPEED Technology Inc.

    Inventor： Hung-Ju Huang ,  Fu-Chou Hsu ,  Chung-Yen Lu

    IPC: G06F11/00 ,  G06F11/22 ,  G06F13/42

    CPC classification number: G06F11/221 ,  G06F11/2205 ,  G06F11/27 ,  G06F13/4282

    Abstract: A System on Chip (SOC) is disclosed. The SOC comprises a first UART controller, a second UART controller, a debug controller, a processor, a UART port, a first multiplexer and a second multiplexer. The first UART controller and the second UART controller have different baud rates. The UART port has a R×D pin coupled to a R×D pin of the second UART controller. The debug controller generates a control signal with a first state and checks whether a received data from the UART controller is equal to a keyword after power-up or a hardware reset. When the received data from the second UART controller is equal to the keyword, the debug controller generates the control signal with the second state, and starts parsing and executing at least one debug command from the second UART controller.

    Abstract translation: 公开了片上系统（SOC）。 该SOC包括第一UART控制器，第二UART控制器，调试控制器，处理器，UART端口，第一多路复用器和第二多路复用器。 第一个UART控制器和第二个UART控制器具有不同的波特率。 UART端口的R×D引脚与第二个UART控制器的R×D引脚相连。 调试控制器产生具有第一状态的控制信号，并检查在上电或硬件复位后，来自UART控制器的接收数据是否等于关键字。 当来自第二UART控制器的接收数据等于关键字时，调试控制器产生具有第二状态的控制信号，并且从第二UART控制器开始解析和执行至少一个调试命令。

    Graphic remoting system with masked DMA and graphic processing method
    8.
    发明授权
    Graphic remoting system with masked DMA and graphic processing method 有权
    具有屏蔽DMA和图形处理方法的图形遥控系统

    公开(公告)号：US09471956B2

    公开(公告)日：2016-10-18

    申请号：US14473607

    申请日：2014-08-29

    Applicant: ASPEED Technology Inc.

    Inventor： Chung-Yen Lu ,  Kuo-Wei Yeh ,  Ming-Chi Bai ,  Lung-Hsiang Kai

    IPC: G09G5/36 ,  G06T1/60 ,  G06T1/20

    CPC classification number: G06T1/60 ,  G06T1/20 ,  G06T2200/28

    Abstract: An embodiment of a graphic remoting system of the present invention includes a network, a server and a client device. The network is applied to a RDP protocol. The server transfers display rendering commands which indicates a destination region through the network. The client device receives the display rendering commands. The client device of the present invention includes at least a graphic render engine, at least a surface, at least a mask generator, a plurality of mask buffer, at least a direct memory access with masks, and a plurality of display buffers. The surface is used for storing an image. The graphic render engine generates the image and stores the image into the surface according to the destination region. The mask buffers is used for storing bit masks; wherein the content values of the mask buffers are indicating updated areas of the image stored in the surface. The mask generator generates the bit masks according to the destination region, and stores the bit masks into the mask buffers. The direct memory access with masks reads the content values of a current mask buffer and a previous mask buffer of the plurality of mask buffers, and copies the image stored in the surface to output a copied image to the display buffer according to the content values of the current mask buffer and the previous mask buffer. The plurality of display buffers receive the copied image from the direct memory access with masks and reconstruct a complete image according to the copied image to output the complete image to a display device.

    Abstract translation: 本发明的图形遥控系统的实施例包括网络，服务器和客户端设备。 该网络应用于RDP协议。 服务器通过网络传送指示目的地区域的显示渲染命令。 客户端设备接收显示渲染命令。 本发明的客户端设备至少包括图形呈现引擎，至少表面，至少掩模生成器，多个掩码缓冲器，至少具有掩码的直接存储器存取和多个显示缓冲器。 表面用于存储图像。 图形渲染引擎生成图像并根据目的地区域将图像存储在表面中。 掩码缓冲器用于存储位掩码; 其中所述掩码缓冲器的内容值指示存储在所述表面中的所述图像的更新区域。 掩码生成器根据目的地区域生成位掩码，并将位掩码存储到掩码缓冲器中。 具有掩码的直接存储器访问读取多个掩码缓冲器中的当前掩码缓冲器和先前掩码缓冲器的内容值，并且复制存储在表面中的图像，以根据内容值的内容值将复印图像输出到显示缓冲器 当前的掩码缓冲区和以前的掩码缓冲区。 多个显示缓冲器从具有掩模的直接存储器访问接收复制的图像，并根据复制的图像重建完整图像，以将完整图像输出到显示装置。

    Method for generating projection image with scaling adjustment and seam cut stitching
    9.
    发明授权
    Method for generating projection image with scaling adjustment and seam cut stitching 有权

    公开(公告)号：US11875473B2

    公开(公告)日：2024-01-16

    申请号：US17347981

    申请日：2021-06-15

    Applicant: ASPEED Technology Inc.

    Inventor： Chung-Yen Lu

    IPC: G06T3/00 ,  H04N23/698 ,  G06T3/40 ,  H04N23/80

    CPC classification number: G06T3/0093 ,  G06T3/0018 ,  G06T3/4038 ,  H04N23/698 ,  H04N23/80

    Abstract: An image processing method for receiving M lens images and generating a projection image is disclosed. The method comprises: determining P optimal warping coefficients of P control regions in the projection image according to a 2D error table and the M lens images from an image capture module; generating M projection images according to the M lens images, a first vertex list and the P optimal warping coefficients; determining a seam for each of N seam regions; and, stitching two overlapping seam images to generate a stitched seam image for each seam region according to its corresponding seam. The 2D error table comprises multiple test warping coefficients and multiple accumulation pixel value differences in the P control regions. The P control regions are respectively located in the N seam regions respectively located in N overlap regions, where M>=2, N>=1 and P>=3.

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