公开(公告)号：US20250110798A1

公开(公告)日：2025-04-03

申请号：US18792235

申请日：2024-08-01

Applicant: ATI TECHNOLOGIES ULC

Inventor： INDRANI PAUL ,  LEONARDO DE PAULA ROSA PIGA ,  MAHESH SUBRAMONY ,  SONU ARORA ,  DONALD CHEREPACHA ,  ADAM N C CLARK

IPC: G06F9/50 ,  G06F1/3203 ,  G06F1/3234 ,  G06F1/324 ,  G06F1/3296 ,  G06F11/30 ,  G06F11/34

Abstract: Methods and apparatus employ a plurality of heterogeneous compute units and a plurality of non-compute units operatively coupled to the plurality of compute units. Power management logic (PML) determines a memory bandwidth level associated with a respective workload running on each of a plurality of heterogeneous compute units on the IC, and adjusts a power level of at least one non-compute unit of a memory system on the IC from a first power level to a second power level, based on the determined memory bandwidth levels. Memory access latency is also taken into account in some examples to adjust a power level of non-compute units.

公开(公告)号：US20220317747A1

公开(公告)日：2022-10-06

申请号：US17219020

申请日：2021-03-31

Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ULC

Inventor： WONJE CHOI ,  MICHAEL J. AUSTIN ,  INDRANI PAUL ,  MEETA SRIVASTAV ,  ALEXANDER SABINO DUENAS

IPC: G06F1/26

Abstract: Power shifting based on bottleneck prediction, including: determining a first plurality of performance metrics for an accelerated processing unit (APU) and a second plurality of performance metrics for a graphics processing unit (GPU); providing the first plurality of performance metrics and the second plurality of performance metrics as an input to a model configured to identify one or more bottlenecks in the APU or the GPU; determining, based on an output of the model, a power distribution between the APU and the GPU; and applying the power distribution.