公开(公告)号：US10749552B2

公开(公告)日：2020-08-18

申请号：US16140364

申请日：2018-09-24

Applicant: Advanced Micro Devices, Inc.

Inventor： Balwinder Singh ,  Milam Paraschou ,  Chad S. Gallun ,  Jeffrey Cooper ,  Dean E. Gonzales ,  Alushulla Jack Ambundo ,  Thomas H. Likens, III ,  Gerald R. Talbot

IPC: H04B1/04 ,  H03M1/80 ,  H01L27/02 ,  H04B1/16

Abstract: Systems, apparatuses, and methods for performing efficient data transfer in a computing system are disclosed. A computing system includes multiple transmitters sending singled-ended data signals to multiple receivers. A termination voltage is generated and sent to the multiple receivers. The termination voltage is coupled to each of signal termination circuitry and signal sampling circuitry within each of the multiple receivers. Any change in the termination voltage affects the termination circuitry and affects comparisons performed by the sampling circuitry. Received signals are reconstructed at the receivers using the received signals, the signal termination circuitry and the signal sampling circuitry.

公开(公告)号：US20200099406A1

公开(公告)日：2020-03-26

申请号：US16140364

申请日：2018-09-24

Applicant: Advanced Micro Devices, Inc.

Inventor： Balwinder Singh ,  Milam Paraschou ,  Chad S. Gallun ,  Jeffrey Cooper ,  Dean E. Gonzales ,  Alushulla Jack Ambundo ,  Thomas H. Likens, III ,  Gerald R. Talbot

IPC: H04B1/04 ,  H04B1/16 ,  H01L27/02 ,  H03M1/80

Abstract: Systems, apparatuses, and methods for performing efficient data transfer in a computing system are disclosed. A computing system includes multiple transmitters sending singled-ended data signals to multiple receivers. A termination voltage is generated and sent to the multiple receivers. The termination voltage is coupled to each of signal termination circuitry and signal sampling circuitry within each of the multiple receivers. Any change in the termination voltage affects the termination circuitry and affects comparisons performed by the sampling circuitry. Received signals are reconstructed at the receivers using the received signals, the signal termination circuitry and the signal sampling circuitry.

公开(公告)号：US10692545B2

公开(公告)日：2020-06-23

申请号：US16140356

申请日：2018-09-24

Applicant: Advanced Micro Devices, Inc.

Inventor： Milam Paraschou ,  Balwinder Singh ,  Gerald R. Talbot ,  Alushulla Jack Ambundo ,  Edoardo Prete ,  Thomas H. Likens, III ,  Michael A. Margules

IPC: G11C7/10 ,  G11C5/14 ,  G11C11/4074 ,  H04L25/02 ,  H03K17/687

Abstract: Systems, apparatuses, and methods for performing efficient data transfer in a computing system are disclosed. A termination voltage generator includes an inverter-based chopper circuit, which uses a first group of an even number of serially connected inverters coupled between the output node of the chopper circuit and the gate terminal of an output pmos transistor. Additionally, a second group of an even number of serially connected inverters is coupled between the output node and the gate terminal of an output nmos transistor. A replica inverter includes two serially connected pmos transistors and two serially connected nmos transistors. Each of one pmos transistor and one nmos transistor receives a generated voltage set as the expected value of the termination voltage. Each of the other pmos transistor and nmos transistor receives an output based on a comparison between the expected value to the output of the replica inverter.

公开(公告)号：US20200098399A1

公开(公告)日：2020-03-26

申请号：US16140356

申请日：2018-09-24

Applicant: Advanced Micro Devices, Inc.

Inventor： Milam Paraschou ,  Balwinder Singh ,  Gerald R. Talbot ,  Alushulla Jack Ambundo ,  Edoardo Prete ,  Thomas H. Likens, III ,  Michael A. Margules

IPC: G11C5/14 ,  H03K17/687 ,  H04L25/02 ,  G11C11/4074

Abstract: Systems, apparatuses, and methods for performing efficient data transfer in a computing system are disclosed. A termination voltage generator includes an inverter-based chopper circuit, which uses a first group of an even number of serially connected inverters coupled between the output node of the chopper circuit and the gate terminal of an output pmos transistor. Additionally, a second group of an even number of serially connected inverters is coupled between the output node and the gate terminal of an output nmos transistor. A replica inverter includes two serially connected pmos transistors and two serially connected nmos transistors. Each of one pmos transistor and one nmos transistor receives a generated voltage set as the expected value of the termination voltage. Each of the other pmos transistor and nmos transistor receives an output based on a comparison between the expected value to the output of the replica inverter.