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公开(公告)号：US20200312382A1
公开(公告)日：2020-10-01
申请号：US16368311
申请日：2019-03-28
Applicant: Advanced Micro Devices, Inc.
Inventor： Milam Paraschou , Jeffrey Cooper
Abstract: Systems, apparatuses, and methods for implementing a sampling circuit with increased headroom are disclosed. A sampling circuit includes at least a pair of input signal transistors connected via their drains to a cross-coupled pair of state nodes. The cross-coupled pair of state nodes are coupled to a tail transistor device via the sources of N-type transistors. When clock goes low, the circuit precharges the cross-coupled pair of state nodes while simultaneously attempting to amplify the difference between the pair of input signals. The amplification is performed by a pair of transistors in series between a source of each input signal transistor and ground. Each gate of the pair of transistors is connected to an inverted clock signal. When clock goes high, the circuit stops precharging and a voltage difference between the pair of input signals is regenerated to create a resulting differential voltage on the pair of state nodes.
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公开(公告)号：US20230134926A1
公开(公告)日：2023-05-04
申请号：US17566199
申请日：2021-12-30
Applicant: Advanced Micro Devices, Inc.
Inventor： Rajesh Kumar , Edoardo Prete , Gerald R. Talbot , Ethan Crain , Tracy J. Feist , Jeffrey Cooper
IPC: H03K19/0175 , H03F3/45
Abstract: Systems, apparatuses, and methods for implementing a combo scheme for direct current (DC) level shifting of signals are disclosed. A receiver circuit receives an input signal on a first interface. The first interface is coupled to a resistor in parallel with a capacitor which passes the input signal to a second interface. Also, the first interface is coupled to a first pair of current sources between ground and a voltage source, and the second interface is coupled to a second pair of current sources between ground and the voltage source. An op-amp drives the current sources based on a difference between a sensed common mode voltage and a reference voltage. Based on this circuit configuration, the receiver circuit is able to prevent baseline wander, perform a DC level shift of the input signal, and achieve linear equalization of the input signal.
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公开(公告)号：US10944368B2
公开(公告)日：2021-03-09
申请号：US16289247
申请日：2019-02-28
Applicant: Advanced Micro Devices, Inc.
Inventor： Milam Paraschou , Jeffrey Cooper
IPC: H03F3/45
Abstract: Systems, apparatuses, and methods for performing offset correction for pseudo differential signaling are disclosed. An apparatus includes at least a sense amplifier and an offset correction circuit. The offset correction circuit generates an offset correction voltage by applying a positive or negative offset to a termination voltage. The offset correction circuit supplies the offset correction voltage to a negative input terminal of the sense amplifier. An input signal voltage is supplied to the positive input terminal of the sense amplifier. The sense amplifier generates an output based on a comparison of the voltages supplied to the positive and negative input terminals.
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公开(公告)号：US20200280290A1
公开(公告)日：2020-09-03
申请号：US16289247
申请日：2019-02-28
Applicant: Advanced Micro Devices, Inc.
Inventor： Milam Paraschou , Jeffrey Cooper
IPC: H03F3/45
Abstract: Systems, apparatuses, and methods for performing offset correction for pseudo differential signaling are disclosed. An apparatus includes at least a sense amplifier and an offset correction circuit. The offset correction circuit generates an offset correction voltage by applying a positive or negative offset to a termination voltage. The offset correction circuit supplies the offset correction voltage to a negative input terminal of the sense amplifier. An input signal voltage is supplied to the positive input terminal of the sense amplifier. The sense amplifier generates an output based on a comparison of the voltages supplied to the positive and negative input terminals.
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公开(公告)号：US12034440B2
公开(公告)日：2024-07-09
申请号：US17566199
申请日：2021-12-30
Applicant: Advanced Micro Devices, Inc.
Inventor： Rajesh Kumar , Edoardo Prete , Gerald R. Talbot , Ethan Crain , Tracy J. Feist , Jeffrey Cooper
IPC: H03K19/01 , H03K19/0175 , H03F3/45
CPC classification number: H03K19/017509 , H03F3/45475
Abstract: Systems, apparatuses, and methods for implementing a combo scheme for direct current (DC) level shifting of signals are disclosed. A receiver circuit receives an input signal on a first interface. The first interface is coupled to a resistor in parallel with a capacitor which passes the input signal to a second interface. Also, the first interface is coupled to a first pair of current sources between ground and a voltage source, and the second interface is coupled to a second pair of current sources between ground and the voltage source. An op-amp drives the current sources based on a difference between a sensed common mode voltage and a reference voltage. Based on this circuit configuration, the receiver circuit is able to prevent baseline wander, perform a DC level shift of the input signal, and achieve linear equalization of the input signal.
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Patent Agency Ranking
公开(公告)号：US11283589B2
公开(公告)日：2022-03-22
申请号：US17128720
申请日：2020-12-21
Applicant: Advanced Micro Devices, Inc. , ATI Technologies ULC
Inventor： Varun Gupta , Milam Paraschou , Gerald R. Talbot , Gurunath Dollin , Damon Tohidi , Eric Ian Carpenter , Chad S. Gallun , Jeffrey Cooper , Hanwoo Cho , Thomas H. Likens, III , Scott F. Dow , Michael J. Tresidder
Abstract: Systems, apparatuses, and methods for implementing a deskewing method for a physical layer interface on a multi-chip module are disclosed. A circuit connected to a plurality of communication lanes trains each lane to synchronize a local clock of the lane with a corresponding global clock at a beginning of a timing window. Next, the circuit symbol rotates each lane by a single step responsive to determining that all of the plurality of lanes have an incorrect symbol alignment. Responsive to determining that some but not all of the plurality of lanes have a correct symbol alignment, the circuit symbol rotates lanes which have an incorrect symbol alignment by a single step. When the end of the timing window has been reached, the circuit symbol rotates lanes which have a correct symbol alignment and adjusts a phase of a corresponding global clock to compensate for missed symbol rotations.
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公开(公告)号：US10749552B2
公开(公告)日：2020-08-18
申请号：US16140364
申请日：2018-09-24
Applicant: Advanced Micro Devices, Inc.
Inventor： Balwinder Singh , Milam Paraschou , Chad S. Gallun , Jeffrey Cooper , Dean E. Gonzales , Alushulla Jack Ambundo , Thomas H. Likens, III , Gerald R. Talbot
Abstract: Systems, apparatuses, and methods for performing efficient data transfer in a computing system are disclosed. A computing system includes multiple transmitters sending singled-ended data signals to multiple receivers. A termination voltage is generated and sent to the multiple receivers. The termination voltage is coupled to each of signal termination circuitry and signal sampling circuitry within each of the multiple receivers. Any change in the termination voltage affects the termination circuitry and affects comparisons performed by the sampling circuitry. Received signals are reconstructed at the receivers using the received signals, the signal termination circuitry and the signal sampling circuitry.
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公开(公告)号：US20200099406A1
公开(公告)日：2020-03-26
申请号：US16140364
申请日：2018-09-24
Applicant: Advanced Micro Devices, Inc.
Inventor： Balwinder Singh , Milam Paraschou , Chad S. Gallun , Jeffrey Cooper , Dean E. Gonzales , Alushulla Jack Ambundo , Thomas H. Likens, III , Gerald R. Talbot
Abstract: Systems, apparatuses, and methods for performing efficient data transfer in a computing system are disclosed. A computing system includes multiple transmitters sending singled-ended data signals to multiple receivers. A termination voltage is generated and sent to the multiple receivers. The termination voltage is coupled to each of signal termination circuitry and signal sampling circuitry within each of the multiple receivers. Any change in the termination voltage affects the termination circuitry and affects comparisons performed by the sampling circuitry. Received signals are reconstructed at the receivers using the received signals, the signal termination circuitry and the signal sampling circuitry.
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公开(公告)号：US10530325B1
公开(公告)日：2020-01-07
申请号：US16118054
申请日：2018-08-30
Applicant: Advanced Micro Devices, Inc. , ATI Technologies ULC
Inventor： Dean E. Gonzales , Xuan Chen , Jeffrey Cooper , Milam Paraschou
Abstract: Systems, apparatuses, and methods for performing efficient data transfer in a computing system are disclosed. A computing system includes multiple transmitters sending singled-ended data signals to multiple receivers. A receiver includes multiple series inductors moved from a signal path to sampling circuitry to a termination path used for impedance matching. The removed direct current (DC) resistances of the inductors in the signal path reduces signal attenuation. The termination path has alternating current (AC) reactances of the inductors, which provide a frequency-dependent termination impedance. This termination impedance provides a positive reflection coefficient for high operating frequencies, which boosts the input signal being received by the sampling circuitry.
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公开(公告)号：US20250007516A1
公开(公告)日：2025-01-02
申请号：US18763572
申请日：2024-07-03
Applicant: Advanced Micro Devices, Inc.
Inventor： Rajesh Kumar , Edoardo Prete , Gerald R. Talbot , Ethan Crain , Tracy J. Feist , Jeffrey Cooper
IPC: H03K19/0175 , H03F3/45
Abstract: Systems, apparatuses, and methods for implementing a combo scheme for direct current (DC) level shifting of signals are disclosed. A receiver circuit receives an input signal on a first interface. The first interface is coupled to a resistor in parallel with a capacitor which passes the input signal to a second interface. Also, the first interface is coupled to a first pair of current sources between ground and a voltage source, and the second interface is coupled to a second pair of current sources between ground and the voltage source. An op-amp drives the current sources based on a difference between a sensed common mode voltage and a reference voltage. Based on this circuit configuration, the receiver circuit is able to prevent baseline wander, perform a DC level shift of the input signal, and achieve linear equalization of the input signal.
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