公开(公告)号：US09606177B2

公开(公告)日：2017-03-28

申请号：US14716215

申请日：2015-05-19

Applicant: Advanced Micro Devices, Inc.

Inventor： Daniel W. Bailey ,  Abhishek Sharma ,  Michael Q. Co

IPC: H03K3/00 ,  G01R31/3177 ,  G01R31/317

CPC classification number: G01R31/3177 ,  G01R31/31727 ,  G01R31/318525 ,  G01R31/318552

Abstract: In one form, a scan flip-flop includes a clock gating cell and a dedicated clock flip-flop. The clock gating cell provides an input clock input signal as a scan clock signal when a scan shift enable signal is active, and provides the input clock signal as a data clock signal when the scan shift enable signal is inactive. The dedicated clock flip-flop stores a data input signal and provides the data input signal, so stored, as a data output signal in response to transitions of the data clock signal, and stores a scan data input signal and provides the scan data input signal, so stored, as the data output signal in response to transitions of the scan clock signal. The clock gating cell may further provide the input clock signal as the data clock signal when both a scan shift enable signal is inactive and a data enable signal is active.

公开(公告)号：US20160341793A1

公开(公告)日：2016-11-24

申请号：US14716215

申请日：2015-05-19

Applicant: Advanced Micro Devices, Inc.

Inventor： Daniel W. Bailey ,  Abhishek Sharma ,  Michael Q. Co

IPC: G01R31/3177 ,  G01R31/317

CPC classification number: G01R31/3177 ,  G01R31/31727 ,  G01R31/318525 ,  G01R31/318552

Abstract: In one form, a scan flip-flop includes a clock gating cell and a dedicated clock flip-flop. The clock gating cell provides an input clock input signal as a scan clock signal when a scan shift enable signal is active, and provides the input clock signal as a data clock signal when the scan shift enable signal is inactive. The dedicated clock flip-flop stores a data input signal and provides the data input signal, so stored, as a data output signal in response to transitions of the data clock signal, and stores a scan data input signal and provides the scan data input signal, so stored, as the data output signal in response to transitions of the scan clock signal. The clock gating cell may further provide the input clock signal as the data clock signal when both a scan shift enable signal is inactive and a data enable signal is active.

Abstract translation: 在一种形式中，扫描触发器包括时钟门控单元和专用时钟触发器。 当扫描移位使能信号有效时，时钟门控单元提供输入时钟输入信号作为扫描时钟信号，并且当扫描移位使能信号无效时，时钟门控单元提供输入时钟信号作为数据时钟信号。 专用时钟触发器存储数据输入信号，并且响应于数据时钟信号的转变而提供数据输入信号，从而存储数据输入信号作为数据输出信号，并存储扫描数据输入信号并提供扫描数据输入信号 ，因此存储，作为响应于扫描时钟信号的转变的数据输出信号。 当扫描移位使能信号无效且数据使能信号有效时，时钟门控单元还可以提供输入时钟信号作为数据时钟信号。

公开(公告)号：US09680450B2

公开(公告)日：2017-06-13

申请号：US14625849

申请日：2015-02-19

Applicant: Advanced Micro Devices, Inc.

Inventor： Daniel W. Bailey

IPC: H03K3/00 ,  H03K3/037 ,  H03K3/356 ,  H03K3/3562

CPC classification number: H03K3/0372 ,  H03K3/356139 ,  H03K3/356173 ,  H03K3/35625

Abstract: In one form, a flip-flop comprises a master latch, a slave latch, and a multiplexer. The master latch has an input for receiving a data input signal, and an output, and operates in transparent and latching modes during respective first and second phases of a clock signal. The slave latch has an input coupled to the output of the master latch, and an output, and operates in the transparent and latching modes during the second and first phases of the clock signal, respectively. The multiplexer has a first input coupled to the output of the slave latch, a second input coupled to the output of the master latch, and an output for providing a data output signal, and provides the first input to the output during the first phase of the clock signal, and the second input to the output during the second phase of the clock signal.

公开(公告)号：US20160248405A1

公开(公告)日：2016-08-25

申请号：US14625849

申请日：2015-02-19

Applicant: Advanced Micro Devices, Inc.

Inventor： Daniel W. Bailey

IPC: H03K3/3562 ,  H03K3/356

CPC classification number: H03K3/0372 ,  H03K3/356139 ,  H03K3/356173 ,  H03K3/35625

Abstract: In one form, a flip-flop comprises a master latch, a slave latch, and a multiplexer. The master latch has an input for receiving a data input signal, and an output, and operates in transparent and latching modes during respective first and second phases of a clock signal. The slave latch has an input coupled to the output of the master latch, and an output, and operates in the transparent and latching modes during the second and first phases of the clock signal, respectively. The multiplexer has a first input coupled to the output of the slave latch, a second input coupled to the output of the master latch, and an output for providing a data output signal, and provides the first input to the output during the first phase of the clock signal, and the second input to the output during the second phase of the clock signal.

Abstract translation: 在一种形式中，触发器包括主锁存器，从锁存器和多路复用器。 主锁存器具有用于接收数据输入信号和输出的输入，并且在时钟信号的相应第一和第二相位期间以透明和锁存模式操作。 从锁存器具有耦合到主锁存器的输出和输出的输入，并且分别在时钟信号的第二和第一相位期间以透明和锁存模式操作。 多路复用器具有耦合到从锁存器的输出的第一输入，耦合到主锁存器的输出的第二输入和用于提供数据输出信号的输出，并且在第一阶段期间将第一输入提供给输出 时钟信号和在时钟信号的第二阶段期间的输出的第二输入。