公开(公告)号：US10275386B2

公开(公告)日：2019-04-30

申请号：US14318065

申请日：2014-06-27

Applicant: Advanced Micro Devices, Inc.

Inventor： Glenn A. Dearth ,  Gerry Talbot

IPC: G06F13/16 ,  G06F13/28 ,  G06F13/42

Abstract: A plurality of registers implemented in association with a memory physical layer interface (PHY) can be used to store one or more instruction words that indicate one or more commands and one or more delays. A training engine implemented in the memory PHY can generate at-speed programmable sequences of commands for delivery to an external memory and to delay the commands based on the one or more delays. The at-speed programmable sequences of commands can be generated based on the one or more instruction words.

公开(公告)号：US09639495B2

公开(公告)日：2017-05-02

申请号：US14318114

申请日：2014-06-27

Applicant: Advanced Micro Devices, Inc.

Inventor： Glenn A. Dearth ,  Gerry Talbot ,  Anwar Kashem ,  Edoardo Prete ,  Brian Amick

IPC: G06F12/00 ,  G06F13/40

CPC classification number: G06F13/4072 ,  G06F13/1689

Abstract: A controller integrated in a memory physical layer interface (PHY) can be used to control training used to configure the memory PHY for communication with an associated external memory such as a dynamic random access memory (DRAM), thereby removing the need to provide training sequences over a data pipeline between a BIOS and the memory PHY. For example, a controller integrated in the memory PHY can control read training and write training of the memory PHY for communication with the external memory based on a training algorithm. The training algorithm may be a seedless training algorithm that converges on a solution for a timing delay and a voltage offset between the memory PHY and the external memory without receiving, from a basic input/output system (BIOS), seed information that characterizes a signal path traversed by training sequences or commands generated by the training algorithm.

公开(公告)号：US20150378956A1

公开(公告)日：2015-12-31

申请号：US14318065

申请日：2014-06-27

Applicant: Advanced Micro Devices, Inc.

Inventor： Glenn A. Dearth ,  Gerry Talbot

IPC: G06F13/42 ,  G06N99/00 ,  G06F13/28

CPC classification number: G06F13/4234 ,  G06F13/1689 ,  G06F13/28

Abstract: A plurality of registers implemented in association with a memory physical layer interface (PHY) can be used to store one or more instruction words that indicate one or more commands and one or more delays. A training engine implemented in the memory PHY can generate at-speed programmable sequences of commands for delivery to an external memory and to delay the commands based on the one or more delays. The at-speed programmable sequences of commands can be generated based on the one or more instruction words.

Abstract translation: 可以使用与存储器物理层接口（PHY）相关联实现的多个寄存器来存储指示一个或多个命令和一个或多个延迟的一个或多个指令字。 在存储器PHY中实现的训练引擎可以生成用于传送到外部存储器的高速可编程命令序列并且基于一个或多个延迟来延迟命令。 可以基于一个或多个指令字来生成高速可编程命令序列。

公开(公告)号：US20150378603A1

公开(公告)日：2015-12-31

申请号：US14318114

申请日：2014-06-27

Applicant: Advanced Micro Devices, Inc.

Inventor： Glenn A. Dearth ,  Gerry Talbot ,  Anwar Kashem ,  Edoardo Prete ,  Brian Amick

IPC: G06F3/06

CPC classification number: G06F13/4072 ,  G06F13/1689

Abstract: A controller integrated in a memory physical layer interface (PHY) can be used to control training used to configure the memory PHY for communication with an associated external memory such as a dynamic random access memory (DRAM), thereby removing the need to provide training sequences over a data pipeline between a BIOS and the memory PHY. For example, a controller integrated in the memory PHY can control read training and write training of the memory PHY for communication with the external memory based on a training algorithm. The training algorithm may be a seedless training algorithm that converges on a solution for a timing delay and a voltage offset between the memory PHY and the external memory without receiving, from a basic input/output system (BIOS), seed information that characterizes a signal path traversed by training sequences or commands generated by the training algorithm.

Abstract translation: 集成在存储器物理层接口（PHY）中的控制器可用于控制用于配置存储器PHY的训练以与诸如动态随机存取存储器（DRAM）的相关联的外部存储器进行通信，由此消除提供训练序列的需要 在BIOS和存储器PHY之间的数据流水线上。 例如，集成在存储器PHY中的控制器可以基于训练算法来控制用于与外部存储器通信的存储器PHY的读取训练和写入训练。 训练算法可以是无核训练算法，其收敛于存储器PHY和外部存储器之间的定时延迟和电压偏移的解，而不从基本输入/输出系统（BIOS）接收表征信号的种子信息 由训练序列生成的训练序列或命令所遍历的路径。