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公开(公告)号:US10247770B2
公开(公告)日:2019-04-02
申请号:US15381992
申请日:2016-12-16
Applicant: Advanced Micro Devices, Inc.
Inventor: Abhay Deshpande , Arun S. Iyer , Prasanth K. Vallur , Girish Anathahally Singrigowda , Stephen V. Kosonocky
Abstract: Various embodiments of a gate oxide breakdown detection technique detect gate oxide degradation due to stress on a per part basis without destroying functional circuits for an intended application. Stress on the gate oxide may be applied while nominal drain currents flow through a device, thereby stressing the device under conditions similar to actual operating conditions. The technique is relatively fast and does not require analog amplifiers or tuning of substantial amounts of other additional circuitry as compared to conventional gate oxide breakdown detection techniques.
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公开(公告)号:US20240210449A1
公开(公告)日:2024-06-27
申请号:US18089057
申请日:2022-12-27
Applicant: Advanced Micro Devices, Inc.
Inventor: Thanapandi Ganesan , Prateek Mishra , Pramod Baliga Kokkada , Rajesh Mangalore Anand , Aniket Bharat Waghide , Animesh Jain , Girish Anathahally Singrigowda , Dhruvin Devangbhai Shah
IPC: G01R19/165
CPC classification number: G01R19/16528
Abstract: A power sensing circuit in a first voltage domain senses an input voltage from a second voltage domain and provides a power OK signal. The maximum supply voltage of the first voltage domain is above a maximum tolerance for devices in the first voltage domain. Accordingly, protection techniques are employed to ensure that the potential difference between any two terminals of devices in the power sensing circuit does not exceed the maximum tolerance limit. The protection techniques utilize reference voltage-based techniques including level shifting and use of protection devices in transistor stacks. An over-voltage tolerant Schmitt trigger circuit is also employed in the power sensing circuit. A trip point device on the input of the power sensing circuit utilizes a programmable bias voltage to adjust the trip point of the power sensing circuit to accommodate different maximum input voltages from the second voltage domain.
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公开(公告)号:US20180172753A1
公开(公告)日:2018-06-21
申请号:US15381992
申请日:2016-12-16
Applicant: Advanced Micro Devices, Inc.
Inventor: Abhay Deshpande , Arun S. Iyer , Prasanth K. Vallur , Girish Anathahally Singrigowda , Stephen V. Kosonocky
CPC classification number: G01R31/2623 , H03K3/0315 , H03K5/159
Abstract: Various embodiments of a gate oxide breakdown detection technique detect gate oxide degradation due to stress on a per part basis without destroying functional circuits for an intended application. Stress on the gate oxide may be applied while nominal drain currents flow through a device, thereby stressing the device under conditions similar to actual operating conditions. The technique is relatively fast and does not require analog amplifiers or tuning of substantial amounts of other additional circuitry as compared to conventional gate oxide breakdown detection techniques.
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