公开(公告)号：US11463084B1

公开(公告)日：2022-10-04

申请号：US17464009

申请日：2021-09-01

Applicant: Advanced Micro Devices, Inc.

Inventor： Thanapandi Ganesan ,  Prateek Mishra ,  Jagadeesh Anathahalli Singrigowda ,  Dhruvin Devangbhai Shah ,  Animesh Jain ,  Girish Anathahalli Singrigowda

IPC: H03K17/687 ,  H03K5/003

Abstract: A level shifting output circuit converts a signal from a core voltage to an I/O voltage without causing voltage overstress on transistor terminals in the level shifting output circuit. The output circuit includes protection transistors to protect various transistors in the output circuit from overvoltage conditions including those transistors coupled to I/O power supply nodes.

公开(公告)号：US20240210449A1

公开(公告)日：2024-06-27

申请号：US18089057

申请日：2022-12-27

Applicant: Advanced Micro Devices, Inc.

Inventor： Thanapandi Ganesan ,  Prateek Mishra ,  Pramod Baliga Kokkada ,  Rajesh Mangalore Anand ,  Aniket Bharat Waghide ,  Animesh Jain ,  Girish Anathahally Singrigowda ,  Dhruvin Devangbhai Shah

IPC: G01R19/165

CPC classification number: G01R19/16528

Abstract: A power sensing circuit in a first voltage domain senses an input voltage from a second voltage domain and provides a power OK signal. The maximum supply voltage of the first voltage domain is above a maximum tolerance for devices in the first voltage domain. Accordingly, protection techniques are employed to ensure that the potential difference between any two terminals of devices in the power sensing circuit does not exceed the maximum tolerance limit. The protection techniques utilize reference voltage-based techniques including level shifting and use of protection devices in transistor stacks. An over-voltage tolerant Schmitt trigger circuit is also employed in the power sensing circuit. A trip point device on the input of the power sensing circuit utilizes a programmable bias voltage to adjust the trip point of the power sensing circuit to accommodate different maximum input voltages from the second voltage domain.

公开(公告)号：US11923852B2

公开(公告)日：2024-03-05

申请号：US17487467

申请日：2021-09-28

Applicant: Advanced Micro Devices, Inc.

Inventor： Prateek Mishra ,  Thanapandi G ,  Jagadeesh Anathahalli Singrigowda ,  Dhruvin Devangbhai Shah ,  Girish Anathahalli Singrigowda ,  Animesh Jain

IPC: H03K3/037 ,  H03K17/081 ,  H03K19/00

CPC classification number: H03K3/037 ,  H03K17/08104 ,  H03K19/0002

Abstract: A voltage level-shifting circuit for an integrated circuit includes an input terminal receiving a voltage signal referenced to an input/output (I/O) voltage level. A transistor overvoltage protection circuit includes a first p-type metal oxide semiconductor (PMOS) transistor includes a source coupled to the second voltage supply, a gate receiving an enable signal, and a drain connected to a central node. A first n-type metal oxide semiconductor (NMOS) transistor includes a drain connected to the central node, a gate connected to the input terminal, and a source connected to an output terminal. A second NMOS transistor includes a drain connected to the input terminal, a gate connected to the central node, and a source connected to the output terminal.

公开(公告)号：US20230098336A1

公开(公告)日：2023-03-30

申请号：US17487467

申请日：2021-09-28

Applicant: Advanced Micro Devices, Inc.

Inventor： Prateek Mishra ,  Thanapandi G ,  Jagadeesh Anathahalli Singrigowda ,  Dhruvin Devangbhai Shah ,  Girish Anathahalli Singrigowda ,  Animesh Jain

IPC: H03K3/037 ,  H03K17/081 ,  H03K19/00

Abstract: A voltage level-shifting circuit for an integrated circuit includes an input terminal receiving a voltage signal referenced to an input/output (PO) voltage level. A transistor overvoltage protection circuit includes a first p-type metal oxide semiconductor (PMOS) transistor includes a source coupled to the second voltage supply, a gate receiving an enable signal, and a drain connected to a central node. A first n-type metal oxide semiconductor (NMOS) transistor includes a drain connected to the central node, a gate connected to the input terminal, and a source connected to an output terminal. A second NMOS transistor includes a drain connected to the input terminal, a gate connected to the central node, and a source connected to the output terminal.