公开(公告)号：US20220188117A1

公开(公告)日：2022-06-16

申请号：US17123270

申请日：2020-12-16

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： JOHN KALAMATIANOS ,  MICHAEL T. CLARK ,  MARIUS EVERS ,  WILLIAM L. WALKER ,  PAUL MOYER ,  JAY FLEISCHMAN ,  JAGADISH B. KOTRA

IPC: G06F9/30 ,  G06F9/52

Abstract: Processor-guided execution of offloaded instructions using fixed function operations is disclosed. Instructions designated for remote execution by a target device are received by a processor. Each instruction includes, as an operand, a target register in the target device. The target register may be an architected virtual register. For each of the plurality of instructions, the processor transmits an offload request in the order that the instructions are received. The offload request includes the instruction designated for remote execution. The target device may be, for example, a processing-in-memory device or an accelerator coupled to a memory.

公开(公告)号：US20240126552A1

公开(公告)日：2024-04-18

申请号：US18393657

申请日：2023-12-21

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： JOHN KALAMATIANOS ,  MICHAEL T. CLARK ,  MARIUS EVERS ,  WILLIAM L. WALKER ,  PAUL MOYER ,  JAY FLEISCHMAN ,  JAGADISH B. KOTRA

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/52

CPC classification number: G06F9/30181 ,  G06F9/30043 ,  G06F9/30098 ,  G06F9/30138 ,  G06F9/3834 ,  G06F9/3877 ,  G06F9/52

Abstract: Processor-guided execution of offloaded instructions using fixed function operations is disclosed. Instructions designated for remote execution by a target device are received by a processor. Each instruction includes, as an operand, a target register in the target device. The target register may be an architected virtual register. For each of the plurality of instructions, the processor transmits an offload request in the order that the instructions are received. The offload request includes the instruction designated for remote execution. The target device may be, for example, a processing-in-memory device or an accelerator coupled to a memory.

公开(公告)号：US20200065108A1

公开(公告)日：2020-02-27

申请号：US16106515

申请日：2018-08-21

Applicant: Advanced Micro Devices, Inc.

Inventor： ANDREJ KOCEV ,  JAY FLEISCHMAN ,  KAI TROESTER ,  JOHNNY C. CHU ,  TIM J. WILKENS ,  NEIL MARKETKAR ,  MICHAEL W. LONG

IPC: G06F9/38 ,  G06F9/30

Abstract: Systems and methods selectively bypass address-generation hardware in processor instruction pipelines. In an embodiment, a processor includes an address-generation stage and an address-generation-bypass-determination unit (ABDU). The ABDU receives a load/store instruction. If an effective address for the load/store instruction is not known at the ABDU, the ABDU routes the load/store instruction via the address-generation stage of the processor. If, however, the effective address of the load/store instruction is known at the ABDU, the ABDU routes the load/store instruction to bypass the address-generation stage of the processor.