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公开(公告)号：US12141066B2
公开(公告)日：2024-11-12
申请号：US17556649
申请日：2021-12-20
Applicant: Advanced Micro Devices, Inc.
IPC: G06F12/08 , G06F12/0811 , G06F12/0817 , G06F12/0891 , G06F13/16
Abstract: A data processing system includes a plurality of coherent masters, a plurality of coherent slaves, and a coherent data fabric. The coherent data fabric has upstream ports coupled to the plurality of coherent masters and downstream ports coupled to the plurality of coherent slaves for selectively routing accesses therebetween. The coherent data fabric includes a probe filter and a directory cleaner. The probe filter is associated with at least one of the downstream ports and has a plurality of entries that store information about each entry. The directory cleaner periodically scans the probe filter and selectively removes a first entry from the probe filter after the first entry is scanned.
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Patent Agency Ranking
公开(公告)号：US11704183B2
公开(公告)日：2023-07-18
申请号：US17544074
申请日：2021-12-07
Applicant: Advanced Micro Devices, Inc.
Inventor： Kedarnath Balakrishnan , James R. Magro , Kevin Michael Lepak , Vilas Sridharan
CPC classification number: G06F11/0772 , G06F11/0727 , G06F11/0751 , G06F11/1004 , G06F11/1068 , H03M13/29
Abstract: A data processor includes provides memory commands to a memory channel according to predetermined criteria. The data processor includes a first error code generation circuit, a second error code generation circuit, and a queue. The first error code generation circuit generates a first type of error code in response to data of a write request. The second error code generation circuit generates a second type of error code for the write request, the second type of error code different from the first type of error code. The queue is coupled to the first error code generation circuit and to the second error code generation circuit, for provides write commands to an interface, the write commands including the data, the first type of error code, and the second type of error code.
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公开(公告)号：US20220091921A1
公开(公告)日：2022-03-24
申请号：US17544074
申请日：2021-12-07
Applicant: Advanced Micro Devices, Inc.
Inventor： Kedarnath Balakrishnan , James R. Magro , Kevin Michael Lepak , Vilas Sridharan
Abstract: A data processor includes provides memory commands to a memory channel according to predetermined criteria. The data processor includes a first error code generation circuit, a second error code generation circuit, and a queue. The first error code generation circuit generates a first type of error code in response to data of a write request. The second error code generation circuit generates a second type of error code for the write request, the second type of error code different from the first type of error code. The queue is coupled to the first error code generation circuit and to the second error code generation circuit, for provides write commands to an interface, the write commands including the data, the first type of error code, and the second type of error code.
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公开(公告)号：US11200106B2
公开(公告)日：2021-12-14
申请号：US16705913
申请日：2019-12-06
Applicant: Advanced Micro Devices, Inc.
Inventor： Kedarnath Balakrishnan , James R. Magro , Kevin Michael Lepak , Vilas Sridharan
Abstract: A data processing system includes a memory channel, a memory coupled to the memory channel, and a data processor. The data processor is coupled to the memory channel and accesses the memory over the memory channel using a packet structure defining a plurality of commands and having corresponding address bits, data bits, and user bits. The data processor communicates with the memory over the memory channel using a first type of error code. In response to a write access request, the data processor calculates a different, second type of error code and appends each bit of the second type of error code as a corresponding one of the user bits. The memory stores the user bits in the memory in response to a write command, and transfers the user bits to the data processor in a read response packet in response to a read command.
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公开(公告)号：US20230195632A1
公开(公告)日：2023-06-22
申请号：US17556649
申请日：2021-12-20
Applicant: Advanced Micro Devices, Inc.
IPC: G06F12/0817 , G06F12/0811 , G06F12/0891 , G06F13/16
CPC classification number: G06F12/0817 , G06F12/0811 , G06F12/0891 , G06F13/1668
Abstract: A data processing system includes a plurality of coherent masters, a plurality of coherent slaves, and a coherent data fabric. The coherent data fabric has upstream ports coupled to the plurality of coherent masters and downstream ports coupled to the plurality of coherent slaves for selectively routing accesses therebetween. The coherent data fabric includes a probe filter and a directory cleaner. The probe filter is associated with at least one of the downstream ports and has a plurality of entries that store information about each entry. The directory cleaner periodically scans the probe filter and selectively removes a first entry from the probe filter after the first entry is scanned.
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公开(公告)号：US20210049062A1
公开(公告)日：2021-02-18
申请号：US16705913
申请日：2019-12-06
Applicant: Advanced Micro Devices, Inc.
Inventor： Kedarnath Balakrishnan , James R. Magro , Kevin Michael Lepak , Vilas Sridharan
Abstract: A data processing system includes a memory channel, a memory coupled to the memory channel, and a data processor. The data processor is coupled to the memory channel and accesses the memory over the memory channel using a packet structure defining a plurality of commands and having corresponding address bits, data bits, and user bits. The data processor communicates with the memory over the memory channel using a first type of error code. In response to a write access request, the data processor calculates a different, second type of error code and appends each bit of the second type of error code as a corresponding one of the user bits. The memory stores the user bits in the memory in response to a write command, and transfers the user bits to the data processor in a read response packet in response to a read command.
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