公开(公告)号：US20250004963A1

公开(公告)日：2025-01-02

申请号：US18217079

申请日：2023-06-30

Applicant: Advanced Micro Devices, Inc.

Inventor： William Peter Ehrett ,  Anthony Gutierrez ,  Vedula Venkata Srikant Bharadwaj ,  Karthik Ramu Sangaiah ,  Prachi Shukla ,  Sriseshan Srikanth ,  Ganesh Dasika ,  John Kalamatianos

IPC: G06F13/36

Abstract: A semiconductor device, referred to herein as a Globally Interconnected Operations (GIO) layer, provides global operations in the form of global data reduction for one or more PE arrays. The GIO layer includes processing elements that perform global data reduction on processing results from one or more PE arrays. The GIO layer includes connectors that allow it to be arranged in a 3D stack with one or more PE arrays, for example, on top of or beneath a PE array. This allows reduction operations to be implemented across PE arrays using an efficient topology with superior flexibility, scalability, latency and/or power characteristics that is customizable for particular use cases at assembly time, without requiring costly and time-consuming redesign of PE arrays, and without being constrained by particular PE array designs.