公开(公告)号：US11625352B2

公开(公告)日：2023-04-11

申请号：US16900632

申请日：2020-06-12

Applicant: Advanced Micro Devices, Inc.

Inventor： Guanhao Shen ,  Ravindra Nath Bhargava ,  Raghava Sravan Adidamu

IPC: G06F13/40

Abstract: A memory controller includes a command queue and an arbiter for selecting entries from the command queue for transmission to a DRAM. The arbiter transacts streaks of consecutive read commands and streaks of consecutive write commands. The arbiter has a current mode indicating the type of commands currently being transacted, and a cross mode indicating the other type. The arbiter is operable to monitor commands in the command queue for the current mode and the cross mode, and in response to designated conditions, send at least one cross-mode command to the memory interface queue while continuing to operate in the current mode. In response to an end streak condition, the arbiter swaps the current mode and the cross mode, and transacts the cross-mode command.

公开(公告)号：US20210357336A1

公开(公告)日：2021-11-18

申请号：US15931825

申请日：2020-05-14

Applicant: Advanced Micro Devices, Inc.

Inventor： Guanhao Shen ,  Ravindra Nath Bhargava ,  Raghava Sravan Adidamu

IPC: G06F13/16

Abstract: A memory controller an arbiter which causes streaks of read commands and streaks of write commands over the memory channel. During a streak, the arbiter monitors an indicator of data bus efficiency of the memory channel. Responsive to the indicator showing that data bus efficiency is less than a designated threshold, the arbiter stops the current streak and start a streak of the other type.

公开(公告)号：US20210390071A1

公开(公告)日：2021-12-16

申请号：US16900632

申请日：2020-06-12

Applicant: Advanced Micro Devices, Inc.

Inventor： Guanhao Shen ,  Ravindra Nath Bhargava ,  Raghava Sravan Adidamu

IPC: G06F13/40

Abstract: A memory controller includes a command queue and an arbiter for selecting entries from the command queue for transmission to a DRAM. The arbiter transacts streaks of consecutive read commands and streaks of consecutive write commands. The arbiter has a current mode indicating the type of commands currently being transacted, and a cross mode indicating the other type. The arbiter is operable to monitor commands in the command queue for the current mode and the cross mode, and in response to designated conditions, send at least one cross-mode command to the memory interface queue while continuing to operate in the current mode. In response to an end streak condition, the arbiter swaps the current mode and the cross mode, and transacts the cross-mode command.