公开(公告)号：US20200081864A1

公开(公告)日：2020-03-12

申请号：US16127607

申请日：2018-09-11

Applicant: Advanced Micro Devices, Inc.

Inventor： David A. Roberts ,  Shenghsun Cho

IPC: G06F15/173 ,  G06F13/16 ,  G06F13/40 ,  G06F12/0862

Abstract: A system is described that performs memory access operations. The system includes a processor in a first node, a memory in a second node, a communication interconnect coupled to the processor and the memory, and an interconnect controller in the first node coupled between the processor and the communication interconnect. Upon executing a multi-line memory access instruction, the processor prepares a memory access operation for accessing, in the memory, a block of data including at least some of each of at least two lines of data. The processor then causes the interconnect controller to use a single remote direct memory access memory transfer to perform the memory access operation for the block of data via the communication interconnect.

公开(公告)号：US11023410B2

公开(公告)日：2021-06-01

申请号：US16127607

申请日：2018-09-11

Applicant: Advanced Micro Devices, Inc.

Inventor： David A. Roberts ,  Shenghsun Cho

IPC: G06F15/173 ,  G06F13/16 ,  G06F13/40 ,  G06F12/0862

Abstract: A system is described that performs memory access operations. The system includes a processor in a first node, a memory in a second node, a communication interconnect coupled to the processor and the memory, and an interconnect controller in the first node coupled between the processor and the communication interconnect. Upon executing a multi-line memory access instruction, the processor prepares a memory access operation for accessing, in the memory, a block of data including at least some of each of at least two lines of data. The processor then causes the interconnect controller to use a single remote direct memory access memory transfer to perform the memory access operation for the block of data via the communication interconnect.

公开(公告)号：US10447273B1

公开(公告)日：2019-10-15

申请号：US16128014

申请日：2018-09-11

Applicant: Advanced Micro Devices, Inc.

Inventor： David A. Roberts ,  Shenghsun Cho

IPC: G06F7/38 ,  H03K19/173 ,  H03K19/177 ,  G06F9/48 ,  G06F11/30 ,  G06F11/34

Abstract: A method for allocating field-programmable gate array (FPGA) resources includes monitoring a first operating metric for one or more computing devices, identifying a first portion of plurality of macro components of a set of one or more FPGA devices in the one or more computing devices, where the first portion is allocated for implementing one or more user defined functions. The method also includes, in response to a first change in the first operating metric, reallocating the first portion of the macro components for implementing a system function associated with the first operating metric, and generating a first notification indicating the reallocation of the first portion.