公开(公告)号：US20140062566A1

公开(公告)日：2014-03-06

申请号：US13963300

申请日：2013-08-09

Applicant: Advanced Micro Devices, Inc.

Inventor： Visvesh S. Sathe ,  Srikanth Arekapudi ,  Charles Ouyang ,  Kyle Viau

IPC: H03K3/57

CPC classification number: H03K3/57 ,  G06F1/04

Abstract: A resonant clock network includes an inductor coupled to the clock network through a plurality of switches. When the clock network enters resonant mode, the turn-on of the switches to couple the inductor to the clock network is staggered. The clock network may be formed of multiple regions, each with its own inductor and switches. The turn-on of switches of each region may be staggered with respect to the turn-on off the switches of the other regions as well as to the turn-on of switches within a region. In addition to staggering the turn-on of the switches when entering the resonant mode, the switches may be turned off in a staggered manner when exiting the resonant mode of operation.

Abstract translation: 谐振时钟网络包括通过多个开关耦合到时钟网络的电感器。 当时钟网络进入谐振模式时，将电感接通到时钟网络的开关是交错的。 时钟网络可以由多个区域形成，每个区域都有自己的电感和开关。 每个区域的开关的接通可以相对于其它区域的开关的导通以及区域内的开关的接通而交错。 除了在进入谐振模式时交错开关的开启之外，当离开谐振工作模式时，开关可以以交错的方式关闭。

公开(公告)号：US20150121041A1

公开(公告)日：2015-04-30

申请号：US14523718

申请日：2014-10-24

Applicant: Advanced Micro Devices, Inc.

Inventor： Ashok Venkatachar ,  Karthik Punukollu ,  Srikanth Arekapudi ,  Samir A. Chitnis ,  Emil Talpes

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/384 ,  G06F9/30094 ,  G06F9/30098 ,  G06F9/30167 ,  G06F9/3838 ,  G06F9/3863 ,  G06F9/3865

Abstract: Described herein are methods and processors for flag renaming in groups to eliminate dependencies of instructions. Decoder and execution units in the processor may be configured to rename flags into groups that allow each group to be treated separately as appropriate. This flag renaming eliminates flag dependencies with respect to instructions. This allows an instruction to write exactly the flags that the instruction wants without having to create merge dependencies. Methods and processors are provided for handling immediate values embedded in instructions. A 16 bit immediate bus and a 4 bit encoding/control bus are added at the interface between decode and execution units. For an 8 or 12 bit immediate, the upper 4 bits of the immediate bus contain the encoding bits. For a 16 bit immediate, the encoding/control bus contains the encoding bits. The encoding/control bus indicates when to look at the top four bits of the immediate bus.

Abstract translation: 这里描述了用于组中的标志重命名以消除指令的依赖性的方法和处理器。 处理器中的解码器和执行单元可以被配置为将标记重新命名为允许每个组在适当时分开对待的组。 该标志重命名消除了关于指令的标志依赖性。 这允许指令准确地写入指令所需的标志，而无需创建合并依赖关系。 提供了方法和处理器来处理嵌入在指令中的立即值。 解码和执行单元之间的接口添加了一个16位立即总线和一个4位编码/控制总线。 对于8位或12位立即数，立即总线的高4位包含编码位。 对于16位立即数，编码/控制总线包含编码位。 编码/控制总线指示何时查看立即总线的前四位。

公开(公告)号：US20160041853A1

公开(公告)日：2016-02-11

申请号：US14452923

申请日：2014-08-06

Applicant: Advanced Micro Devices, Inc.

Inventor： Srikanth Arekapudi ,  Emil Talpes ,  Sahil Arora

IPC: G06F9/54 ,  G06F9/48

CPC classification number: G06F9/542 ,  G06F9/3828 ,  G06F9/4881

Abstract: A processor includes an execution unit to execute instructions and a scheduler unit to store a queue of instructions for execution by the execution unit. The scheduler unit includes a wake array including a plurality of source slots to store source identifiers for sources associated with the instructions, a picker to schedule a particular instruction for execution in the execution unit, broadcast a destination identifier associated with the particular instruction to a first subset of the source slots, and a delay element to receive the destination identifier broadcast by the picker and communicate a delayed version of the destination identifier to a second subset of the source slots different from the first subset.

Abstract translation: 处理器包括执行指令的执行单元和用于存储由执行单元执行的指令队列的调度器单元。 调度器单元包括包括多个源时隙的唤醒阵列，用于存储与指令相关联的源的源标识符;选择器，用于调度用于在执行单元中执行的特定指令;将与特定指令相关联的目的地标识符广播到第一 源时隙的子集，以及延迟元件，用于接收由选择器广播的目的地标识符，并将目的地标识符的延迟版本传送到与第一子集不同的源时隙的第二子集。

公开(公告)号：US11599359B2

公开(公告)日：2023-03-07

申请号：US16877112

申请日：2020-05-18

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Arun A. Nair ,  Ashok T. Venkatachar ,  Emil Talpes ,  Srikanth Arekapudi ,  Rajesh Kumar Arunachalam

IPC: G06F9/30 ,  G06F9/38

Abstract: A processor in a data processing system includes a master-shadow physical register file and a renaming unit. The master-shadow physical register file has a master storage coupled to shadow storage. The renaming unit is coupled to the master-shadow physical register file. Based on an occurrence of shadow transfer activation conditions verified by the renaming unit, data in the master storage is transferred from the master storage to the shadow storage for storage. Data is transferred from the shadow storage back to the master storage based on the occurrence of a shadow-to-master transfer event, which includes, for example, a flush of the master storage by the processor.

公开(公告)号：US09652305B2

公开(公告)日：2017-05-16

申请号：US14452923

申请日：2014-08-06

Applicant: Advanced Micro Devices, Inc.

Inventor： Srikanth Arekapudi ,  Emil Talpes ,  Sahil Arora

IPC: G06F9/44 ,  G06F9/54 ,  G06F9/48

CPC classification number: G06F9/542 ,  G06F9/3828 ,  G06F9/4881

Abstract: A processor includes an execution unit to execute instructions and a scheduler unit to store a queue of instructions for execution by the execution unit. The scheduler unit includes a wake array including a plurality of source slots to store source identifiers for sources associated with the instructions, a picker to schedule a particular instruction for execution in the execution unit, broadcast a destination identifier associated with the particular instruction to a first subset of the source slots, and a delay element to receive the destination identifier broadcast by the picker and communicate a delayed version of the destination identifier to a second subset of the source slots different from the first subset.

公开(公告)号：US08941432B2

公开(公告)日：2015-01-27

申请号：US13963300

申请日：2013-08-09

Applicant: Advanced Micro Devices, Inc.

Inventor： Visvesh S. Sathe ,  Srikanth Arekapudi ,  Charles Ouyang ,  Kyle Viau

IPC: H03K3/00 ,  H03K3/57 ,  G06F1/04

CPC classification number: H03K3/57 ,  G06F1/04

Abstract: A resonant clock network includes an inductor coupled to the clock network through a plurality of switches. When the clock network enters resonant mode, the turn-on of the switches to couple the inductor to the clock network is staggered. The clock network may be formed of multiple regions, each with its own inductor and switches. The turn-on of switches of each region may be staggered with respect to the turn-on off the switches of the other regions as well as to the turn-on of switches within a region. In addition to staggering the turn-on of the switches when entering the resonant mode, the switches may be turned off in a staggered manner when exiting the resonant mode of operation.

Abstract translation: 谐振时钟网络包括通过多个开关耦合到时钟网络的电感器。 当时钟网络进入谐振模式时，将电感接通到时钟网络的开关是交错的。 时钟网络可以由多个区域形成，每个区域都有自己的电感和开关。 每个区域的开关的接通可以相对于其它区域的开关的导通以及区域内的开关的接通而交错。 除了在进入谐振模式时交错开关的开启之外，当离开谐振工作模式时，开关可以以交错的方式关闭。