公开(公告)号：US20160041853A1

公开(公告)日：2016-02-11

申请号：US14452923

申请日：2014-08-06

Applicant: Advanced Micro Devices, Inc.

Inventor： Srikanth Arekapudi ,  Emil Talpes ,  Sahil Arora

IPC: G06F9/54 ,  G06F9/48

CPC classification number: G06F9/542 ,  G06F9/3828 ,  G06F9/4881

Abstract: A processor includes an execution unit to execute instructions and a scheduler unit to store a queue of instructions for execution by the execution unit. The scheduler unit includes a wake array including a plurality of source slots to store source identifiers for sources associated with the instructions, a picker to schedule a particular instruction for execution in the execution unit, broadcast a destination identifier associated with the particular instruction to a first subset of the source slots, and a delay element to receive the destination identifier broadcast by the picker and communicate a delayed version of the destination identifier to a second subset of the source slots different from the first subset.

Abstract translation: 处理器包括执行指令的执行单元和用于存储由执行单元执行的指令队列的调度器单元。 调度器单元包括包括多个源时隙的唤醒阵列，用于存储与指令相关联的源的源标识符;选择器，用于调度用于在执行单元中执行的特定指令;将与特定指令相关联的目的地标识符广播到第一 源时隙的子集，以及延迟元件，用于接收由选择器广播的目的地标识符，并将目的地标识符的延迟版本传送到与第一子集不同的源时隙的第二子集。

公开(公告)号：US10127044B2

公开(公告)日：2018-11-13

申请号：US14522831

申请日：2014-10-24

Applicant: Advanced Micro Devices, Inc.

Inventor： Douglas Williams ,  Sahil Arora ,  Nikhil Gupta ,  Wei-Yu Chen ,  Debjit Das Sarma ,  Marius Evers

IPC: G06F9/38 ,  G06F9/30

Abstract: A processor, a device, and a non-transitory computer readable medium for performing branch prediction in a processor are presented. The processor includes a front end unit. The front end unit includes a level 1 branch target buffer (BTB), a BTB index predictor (BIP), and a level 1 hash perceptron (HP). The BTB is configured to predict a target address. The BIP is configured to generate a prediction based on a program counter and a global history, wherein the prediction includes a speculative partial target address, a global history value, a global history shift value, and a way prediction. The HP is configured to predict whether a branch instruction is taken or not taken.

公开(公告)号：US09652305B2

公开(公告)日：2017-05-16

申请号：US14452923

申请日：2014-08-06

Applicant: Advanced Micro Devices, Inc.

Inventor： Srikanth Arekapudi ,  Emil Talpes ,  Sahil Arora

IPC: G06F9/44 ,  G06F9/54 ,  G06F9/48

CPC classification number: G06F9/542 ,  G06F9/3828 ,  G06F9/4881

Abstract: A processor includes an execution unit to execute instructions and a scheduler unit to store a queue of instructions for execution by the execution unit. The scheduler unit includes a wake array including a plurality of source slots to store source identifiers for sources associated with the instructions, a picker to schedule a particular instruction for execution in the execution unit, broadcast a destination identifier associated with the particular instruction to a first subset of the source slots, and a delay element to receive the destination identifier broadcast by the picker and communicate a delayed version of the destination identifier to a second subset of the source slots different from the first subset.

公开(公告)号：US20150121050A1

公开(公告)日：2015-04-30

申请号：US14522831

申请日：2014-10-24

Applicant: Advanced Micro Devices, Inc.

Inventor： Douglas Williams ,  Sahil Arora ,  Nikhil Gupta ,  Wei-Yu Chen ,  Debjit Das Sarma ,  Marius Evers

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3806 ,  G06F9/30058 ,  G06F9/3848

Abstract: A processor, a device, and a non-transitory computer readable medium for performing branch prediction in a processor are presented. The processor includes a front end unit. The front end unit includes a level 1 branch target buffer (BTB), a BTB index predictor (BIP), and a level 1 hash perceptron (HP). The BTB is configured to predict a target address. The BIP is configured to generate a prediction based on a program counter and a global history, wherein the prediction includes a speculative partial target address, a global history value, a global history shift value, and a way prediction. The HP is configured to predict whether a branch instruction is taken or not taken.

Abstract translation: 提出了一种用于在处理器中执行分支预测的处理器，设备和非暂时性计算机可读介质。 处理器包括前端单元。 前端单元包括1级分支目标缓冲器（BTB），BTB索引预测器（BIP）和1级散列感知器（HP）。 BTB被配置为预测目标地址。 BIP被配置为基于程序计数器和全局历史生成预测，其中预测包括推测性部分目标地址，全局历史值，全局历史偏移值和路径预测。 HP配置为预测是否采用分支指令。