公开(公告)号：US12153487B1

公开(公告)日：2024-11-26

申请号：US18083218

申请日：2022-12-16

Applicant: Advanced Micro Devices, Inc.

Inventor： Tim Perley ,  Alexander Nozik ,  Siddharth K. Shah

IPC: G06F11/00 ,  G06F11/07

Abstract: The disclosed computer-implemented method includes receiving, by a first circuit subsystem, a hardware error signal and storing, in response to the hardware error signal, a signal state of the first circuit subsystem in a reset-persistent register. The method also includes sending, by the first circuit subsystem, the hardware error signal to a second circuit subsystem. Various other methods, systems, and computer-readable media are also disclosed.

公开(公告)号：US12072378B2

公开(公告)日：2024-08-27

申请号：US16707336

申请日：2019-12-09

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Tim Perley

IPC: G01R31/3177 ,  G06F13/40 ,  G01R31/3185 ,  G06F11/07 ,  G06F11/26 ,  G06F11/36

CPC classification number: G01R31/3177 ,  G06F13/4027 ,  G01R31/3185 ,  G06F11/079 ,  G06F11/26 ,  G06F11/3656 ,  G06F11/3664

Abstract: An integrated circuit (IC) includes a debug controller, a debug state machine (DSM), and an extended performance monitor counter (EPMC). The debug controller that selectively outputs debug data on a debug interconnect. The DSM identifies an event based on the debug data and an event list and outputs a DSM indication that identifies the event. The EPMC indicates a plurality of detected events including the identified event. The EPMC indicates the identified event in response to the DSM indication.