公开(公告)号：US07138829B1

公开(公告)日：2006-11-21

申请号：US10990032

申请日：2004-11-16

申请人： Ajay Dalvi

发明人： Ajay Dalvi

IPC分类号： H03K19/177 ,  H03K19/00

CPC分类号： H03K19/177 ,  G01R31/3016 ,  G01R31/31725

摘要： A system and method for measuring the timing requirements of a sequential logic element of a programmable logic device. The sequential logic element has a first data terminal, an output terminal, and a clock terminal. A first synchronous element is coupled to the data terminal through a first delay element. The first synchronous element is clocked by a clock signal and receives an alternating test signal. A second synchronous element is coupled to the clock terminal through a second delay element of an input-output block. The second synchronous element is also clocked by the clock signal and receives the alternating test signal. The output terminal of the sequential logic element is monitored by a tester or by logic configured in the fabric of the programmable logic device to determine when the logic state changes as the delay of the first or second delay element is selectively varied.

摘要翻译： 一种用于测量可编程逻辑器件的顺序逻辑元件的时序要求的系统和方法。 顺序逻辑元件具有第一数据端子，输出端子和时钟端子。 第一同步元件通过第一延迟元件耦合到数据终端。 第一同步元件由时钟信号计时，并接收交替的测试信号。 第二同步元件通过输入 - 输出块的第二延迟元件耦合到时钟端子。 第二同步元件也由时钟信号计时并接收交替测试信号。 顺序逻辑元件的输出端子由测试器或由可编程逻辑器件的结构中配置的逻辑监视，以确定当第一或第二延迟元件的延迟被选择性地变化时逻辑状态何时改变。

公开(公告)号：US07305604B1

公开(公告)日：2007-12-04

申请号：US11072871

申请日：2005-03-04

申请人： Himanshu J. Verma ,  Ajay Dalvi ,  Paul A. Swartz

发明人： Himanshu J. Verma ,  Ajay Dalvi ,  Paul A. Swartz

IPC分类号： G01R31/28

CPC分类号： H03K19/1774 ,  H03K19/17744

摘要： First and second clock signals are provided to first and second sequential circuits, where the first and second clock signals are inversely coupled to logic high and low levels for clocking of the first and second sequential circuits. A third sequential circuit is clocked responsive to a first output from the first sequential circuit and receives first signature data. A fourth sequential circuit is clocked responsive to a second output from the second sequential circuit and receives second signature data. A third output from the third sequential circuit is monitored responsive to the first signature data and the first output. A fourth output from the fourth sequential circuit is monitored responsive to the second signature data and the second output. Whether the first clock signal and the second clock signal are phase aligned may be determined responsive to the third output and the fourth output.

摘要翻译： 第一和第二时钟信号被提供给第一和第二顺序电路，其中第一和第二时钟信号反向耦合到逻辑高电平和低电平以用于第一和第二顺序电路的时钟。 第三顺序电路响应于来自第一顺序电路的第一输出而被响应并接收第一签名数据。 响应于来自第二顺序电路的第二输出而对第四顺序电路进行时钟响应，并接收第二签名数据。 响应于第一签名数据和第一输出来监视来自第三顺序电路的第三输出。 响应于第二签名数据和第二输出来监视来自第四顺序电路的第四输出。 可以响应于第三输出和第四输出来确定第一时钟信号和第二时钟信号是否相位对准。

公开(公告)号：US08121240B1

公开(公告)日：2012-02-21

申请号：US10990045

申请日：2004-11-16

申请人： Ajay Dalvi

发明人： Ajay Dalvi

IPC分类号： H04L7/00 ,  H04L25/00 ,  H04L25/40

CPC分类号： H04L1/205 ,  G01R31/31709

摘要： Phase shift is added between a uttering clock signal and a data bit stream clocked by the clock signal. The phase shift is adjusted until half the data bits are captured (counted) over a measurement period. Adding this amount of phase shift between the clock and data signals centers the average clock edge placement. In a particular embodiment, counters, each having N bits where N is an integer, are used to count clock pulses and data bits. When one counter is full and the most-significant bit on the other counter goes high, the phase shift between the data and clock signal places the average clock edge at the data bit edge.

摘要翻译： 在发声时钟信号和由时钟信号定时的数据比特流之间增加相移。 调整相移，直到在测量周期内捕获（计数）数据位的一半。 在时钟和数据信号之间增加这种相移量将平均时钟边沿放置居中。 在特定实施例中，每个具有N位的计数器，其中N是整数，用于对时钟脉冲和数据位进行计数。 当一个计数器已满并且另一个计数器的最高有效位变为高电平时，数据和时钟信号之间的相移将平均时钟沿置于数据位沿。

公开(公告)号：US07370245B1

公开(公告)日：2008-05-06

申请号：US11066685

申请日：2005-02-25

申请人： Himanshu J. Verma ,  Ajay Dalvi ,  Paul A. Swartz

发明人： Himanshu J. Verma ,  Ajay Dalvi ,  Paul A. Swartz

IPC分类号： G06K5/04

CPC分类号： H03K3/0315

摘要： Cross-correlation of delay line characteristics is described. An integrated circuit for cross-correlation testing includes: a first ring oscillator and a second ring oscillator. The first ring oscillator includes a first test circuit, and the second ring oscillator includes a second test circuit. The first test circuit is coupled via first programmable interconnects to first ring oscillator circuitry, and the second test circuit is coupled via second programmable interconnects to second ring oscillator circuitry. The first test circuit includes a first programmable delay line, and the second test circuit includes a second programmable delay line. The first test circuit and the second test circuit are configured to provide separately controllable outputs for cross-correlation as between the first programmable delay line and the second programmable delay line.

摘要翻译： 描述了延迟线特性的互相关。 用于互相关测试的集成电路包括：第一环形振荡器和第二环形振荡器。 第一环形振荡器包括第一测试电路，第二环形振荡器包括第二测试电路。 第一测试电路通过第一可编程互连耦合到第一环形振荡器电路，并且第二测试电路经由第二可编程互连耦合到第二环形振荡器电路。 第一测试电路包括第一可编程延迟线，第二测试电路包括第二可编程延迟线。 第一测试电路和第二测试电路被配置为在第一可编程延迟线和第二可编程延迟线之间提供用于互相关的单独可控的输出。