公开(公告)号：US07353400B1

公开(公告)日：2008-04-01

申请号：US09376654

申请日：1999-08-18

Applicant: Alan Folmsbee

Inventor： Alan Folmsbee

IPC: G11C29/00 ,  H04L9/32 ,  G06F11/30 ,  G06F12/14

CPC classification number: G06F21/72 ,  G06F11/08 ,  G06F21/14 ,  G06F21/54 ,  G06F21/73 ,  G11C2029/0411

Abstract: A CPU is provided with an ability to modify its operation, with respect to error correction, as a programmable feature. An error correction scheme is selected to be performed by the error correcting circuit. The compiled program may have intentionally introduced errors which are predictably corrected by the selected error correction scheme. When a program is compiled, the program is modified by the intentional insertion of errors which would result from the execution of the program. By providing error correction schema selected during program compilation, errors can be inserted in the program code, but are handled in a predictable manner by the error correction.

Abstract translation: CPU具有修改作为可编程特征的关于纠错的操作的能力。 纠错方案选择由纠错电路执行。 所编译的程序可能有意引入通过所选择的纠错方案可预测地校正的错误。 当编译程序时，通过有意插入由程序执行导致的错误来修改程序。 通过提供在程序编译期间选择的纠错模式，错误可以插入到程序代码中，但是可以通过错误校正以可预测的方式进行处理。

公开(公告)号：US06665796B1

公开(公告)日：2003-12-16

申请号：US09377299

申请日：1999-08-18

Applicant: Alan Folmsbee

Inventor： Alan Folmsbee

IPC: G06F124

CPC classification number: G06F9/3017 ,  G06F9/30145 ,  G06F9/30174 ,  G06F21/14 ,  G06F21/32

Abstract: A CPU executes program instructions which result in valid and invalid intermediate results. By selecting the desired intermediate results, a program is able to be successfully executed. Analysis of the intermediate results must avoid plausible wrong results. A programmable feature allows the instruction decoder to provide plural answers, including plausible wrong answers. Instruction output selection logic selects a predetermined buffer, and this permits further microprocessor operation with the correct intermediate result.

Abstract translation: CPU执行程序指令，导致有效和无效的中间结果。 通过选择所需的中间结果，可以成功执行程序。 对中间结果的分析必须避免出现合理的错误结果。 可编程功能允许指令解码器提供复数答案，包括合理的错误答案。 指令输出选择逻辑选择预定的缓冲器，并且这允许以正确的中间结果进一步的微处理器操作。

公开(公告)号：US06609201B1

公开(公告)日：2003-08-19

申请号：US09376655

申请日：1999-08-18

Applicant: Alan Folmsbee

Inventor： Alan Folmsbee

IPC: G06F124

CPC classification number: G06F9/3822 ,  G06F9/30145 ,  G06F9/30178 ,  G06F9/30196 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/3857 ,  G06F21/123 ,  G09C1/00 ,  H04L9/0838 ,  H04L9/0894 ,  H04L2209/125 ,  H04L2209/34

Abstract: A CPU is provided with an ability to modify its operation in accordance with an encryption key. When a program is compiled, the program is modified in order that execution may be performed with the CPU changes with respect to pipelined instruction routing. Logic on the CPU is able to route a subset of the register bits, and selects destination logic gates in the microprocessor in a manner consistent with a programmable instruction decoder. This in turn establishes an instruction buffer interdependency.

Abstract translation: CPU具有根据加密密钥修改其操作的能力。 当编译程序时，修改程序，以便可以执行CPU相对于流水线指令路由的改变。 CPU上的逻辑能够路由寄存器位的子集，并以与可编程指令解码器一致的方式在微处理器中选择目标逻辑门。 这又建立了指令缓冲区相互依赖关系。

公开(公告)号：US06308256B1

公开(公告)日：2001-10-23

申请号：US09377297

申请日：1999-08-18

Applicant: Alan Folmsbee

Inventor： Alan Folmsbee

IPC: G06F930

CPC classification number: G09C1/00 ,  G06F9/30145 ,  G06F9/30178 ,  G06F9/3867 ,  G06F21/123 ,  G06F21/72 ,  G06F2207/7219 ,  G06F2211/007 ,  G06F2221/0744 ,  H04L9/06 ,  H04L9/0844 ,  H04L9/0894 ,  H04L2209/12 ,  H04L2209/125 ,  H04L2209/16 ,  H04L2209/34

Abstract: A CPU is provided with an ability to modify its operation in accordance with an encryption key. When a program is compiled, the program is modified in order that execution may be performed with the CPU with its operation modified. As a result, it is unnecessary to decrypt the program into standard op codes prior to execution. The keyed program operation permits secure transfer of program data through open channels such as the Internet. A programmable instruction decoder programmable decodes encrypted instruction op codes, without decrypting them into standard op codes. Logic is used to accomplish network handshaking. The network handshaking further used to provide additional key information for continued operation the CPU.

Abstract translation: CPU具有根据加密密钥修改其操作的能力。 当编译程序时，修改程序，以便可以在修改操作的情况下执行CPU。 因此，在执行之前不需要将程序解码为标准操作码。 密钥编程操作允许通过诸如因特网之类的开放信道安全地传送程序数据。 可编程指令解码器可编程解码加密指令操作码，而不将其解密为标准操作码。 逻辑用于完成网络握手。 网络握手进一步用于提供附加的密钥信息，以便继续操作CPU。

公开(公告)号：US07225322B2

公开(公告)日：2007-05-29

申请号：US10688247

申请日：2003-10-16

Applicant: Alan Folmsbee

Inventor： Alan Folmsbee

IPC: G06F9/40

CPC classification number: G06F9/3017 ,  G06F9/30145 ,  G06F9/30174 ,  G06F21/14 ,  G06F21/32

Abstract: A CPU executes program instructions which result in valid and invalid intermediate results. By selecting the desired intermediate results, a program is able to be successfully executed. Analysis of the intermediate results must avoid plausible wrong results. A programmable feature allows the instruction decoder to provide plural answers, including plausible wrong answers. Instruction output selection logic selects a predetermined buffer, and this permits further microprocessor operation with the correct intermediate result.

Abstract translation: CPU执行程序指令，导致有效和无效的中间结果。 通过选择所需的中间结果，可以成功执行程序。 对中间结果的分析必须避免出现合理的错误结果。 可编程功能允许指令解码器提供复数答案，包括合理的错误答案。 指令输出选择逻辑选择预定的缓冲器，并且这允许以正确的中间结果进一步的微处理器操作。

公开(公告)号：US06757831B1

公开(公告)日：2004-06-29

申请号：US09377344

申请日：1999-08-18

Applicant: Alan Folmsbee

Inventor： Alan Folmsbee

IPC: G06F124

CPC classification number: G06F9/30181 ,  G06F9/30145 ,  G06F21/123 ,  G06F21/14 ,  G06F21/71

Abstract: A CPU is provided with an ability to modify its operation in accordance with an encryption key. When a program is compiled, the program is modified in order that execution may be performed with the CPU with its operation modified. In order to execute program instructions, the buffer interdependencies must match that expected by the compiler. This makes analysis of the program operation extremely difficult. The instruction buffer on a keyed microprocessor contains logic which is able to route a subset of the instruction bits on the microprocessor. This selects destination logic gates in the microprocessor which eventually reach a programmable instruction decoder and an instruction buffer interdependency checking logic block.

Abstract translation: CPU具有根据加密密钥修改其操作的能力。 当编译程序时，修改程序，以便可以在修改操作的情况下执行CPU。 为了执行程序指令，缓冲区相互依赖性必须与编译器预期的相匹配。 这使得对程序操作的分析非常困难。 密钥微处理器上的指令缓冲器包含能够在微处理器上路由指令位子集的逻辑。 这选择微处理器中的目的地逻辑门，其最终到达可编程指令解码器和指令缓冲器相互依赖性检查逻辑块。

公开(公告)号：US06598166B1

公开(公告)日：2003-07-22

申请号：US09377343

申请日：1999-08-18

Applicant: Alan Folmsbee

Inventor： Alan Folmsbee

IPC: H04L900

CPC classification number: G09C1/00 ,  G06F21/125 ,  G06F21/14 ,  G06F21/72 ,  G06F21/73 ,  G06F21/76 ,  H04L9/0838 ,  H04L9/0894 ,  H04L2209/12 ,  H04L2209/125 ,  H04L2209/34

Abstract: A CPU is provided with an ability to modify its operation in accordance with an encryption key which is used to compile software to be executed on the CPU. When a program is compiled for the CPU, the program is modified in order that execution may be performed with the CPU having its operation modified to accommodate the encrypted format of the software. Logic architecture is able to shift the basic op code execution function, and the logic circuitry permits modifying operation of the microprocessor in accordance with logic instruction op codes stored in distributed memory locations. This logic circuitry is configurable in accordance with the received logic instructions during the execution of a program, and it is unnecessary to decrypt the program into standard op codes prior to execution.

Abstract translation: CPU具有根据用于编译要在CPU上执行的软件的加密密钥来修改其操作的能力。 当为CPU编译程序时，修改程序，以便可以执行修改其操作的CPU以适应软件的加密格式。 逻辑架构能够移动基本的操作码执行功能，并且逻辑电路允许根据存储在分布式存储器位置中的逻辑指令操作代码修改微处理器的操作。 该逻辑电路可以在程序执行期间根据所接收的逻辑指令进行配置，并且在执行之前无需将程序解码为标准操作码。

公开(公告)号：US07469344B2

公开(公告)日：2008-12-23

申请号：US10850757

申请日：2004-05-21

Applicant: Alan Folmsbee

Inventor： Alan Folmsbee

IPC: G06F9/00

CPC classification number: G06F9/30181 ,  G06F9/30145 ,  G06F21/123 ,  G06F21/14 ,  G06F21/71

Abstract: A CPU is provided with an ability to modify its operation in accordance with an encryption key. When a program is compiled, the program is modified in order that execution may be performed with the CPU with its operation modified. In order to execute program instructions, the buffer interdependencies must match that expected by the compiler. This makes analysis of the program operation extremely difficult. The instruction buffer on a keyed microprocessor contains logic which is able to route a subset of the instruction bits on the microprocessor. This selects destination logic gates in the microprocessor which eventually reach a programmable instruction decoder and an instruction buffer interdependency checking logic block.

Abstract translation: CPU具有根据加密密钥修改其操作的能力。 当编译程序时，修改程序，以便可以在修改操作的情况下执行CPU。 为了执行程序指令，缓冲区相互依赖性必须与编译器预期的相匹配。 这使得对程序操作的分析非常困难。 密钥微处理器上的指令缓冲器包含能够在微处理器上路由指令位子集的逻辑。 这选择微处理器中的目的地逻辑门，其最终到达可编程指令解码器和指令缓冲器相互依赖性检查逻辑块。

公开(公告)号：US20050005157A1

公开(公告)日：2005-01-06

申请号：US10850757

申请日：2004-05-21

Applicant: Alan Folmsbee

Inventor： Alan Folmsbee

IPC: G06F9/30 ,  G06F9/318 ,  G06F21/00 ,  H04L9/00

CPC classification number: G06F9/30181 ,  G06F9/30145 ,  G06F21/123 ,  G06F21/14 ,  G06F21/71

Abstract: A CPU is provided with an ability to modify its operation in accordance with an encryption key. When a program is compiled, the program is modified in order that execution may be performed with the CPU with its operation modified. In order to execute program instructions, the buffer interdependencies must match that expected by the compiler. This makes analysis of the program operation extremely difficult. The instruction buffer on a keyed microprocessor contains logic which is able to route a subset of the instruction bits on the microprocessor. This selects destination logic gates in the microprocessor which eventually reach a programmable instruction decoder and an instruction buffer interdependency checking logic block.

Abstract translation: CPU具有根据加密密钥修改其操作的能力。 当编译程序时，修改程序，以便可以在修改操作的情况下执行CPU。 为了执行程序指令，缓冲区相互依赖性必须与编译器预期的相匹配。 这使得对程序操作的分析非常困难。 密钥微处理器上的指令缓冲器包含能够在微处理器上路由指令位子集的逻辑。 这选择微处理器中的目的地逻辑门，其最终到达可编程指令解码器和指令缓冲器相互依赖性检查逻辑块。

公开(公告)号：US06675298B1

公开(公告)日：2004-01-06

申请号：US09377298

申请日：1999-08-18

Applicant: Alan Folmsbee

Inventor： Alan Folmsbee

IPC: G06F124

CPC classification number: G06F21/72 ,  G06F9/30145 ,  G06F9/30178 ,  G06F9/30196 ,  G06F21/123 ,  G06F21/125 ,  G06F21/75 ,  G06F21/77 ,  G06F2207/7219

Abstract: A CPU is provided with an ability to modify its operation in accordance with an encryption key. When a program is compiled, the program is modified in order that execution may be performed by the CPU with modified op codes. As a result, it is unnecessary to decrypt the program into standard op codes prior to execution. The modified op codes are provided with surplus bits, causing an increase in op code length, and the output of data results is provided in blocks of several words. The internal allocations of signals and logic gates is made key dependent to further foil the efforts of adversaries who may attempt to understand the program instructions.

Abstract translation: CPU具有根据加密密钥修改其操作的能力。 当编译程序时，修改程序，以便可以由具有修改的操作码的CPU执行执行。 因此，在执行之前不需要将程序解码为标准操作码。 经修改的操作码被提供有多余的位，导致操作码长度的增加，数据结果的输出以多个字的块提供。 信号和逻辑门的内部分配是关键依赖的，以进一步削弱可能尝试了解程序指令的对手的努力。