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公开(公告)号：US11598830B1
公开(公告)日：2023-03-07
申请号：US17653484
申请日：2022-03-04
Applicant: Allegro MicroSystems, LLC
Inventor： Sundar Chetlur , Maxim Klebanov , Yen Ting Liu , Paolo Campiglio
IPC: G01R33/09
Abstract: Methods and apparatus for a sensor including a series of tunneling magnetoresistance (TMR) pillars and a heatsink adjacent to at least one of the TMR pillars, where the heatsink comprises Titanium Nitride (TiN).
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公开(公告)号：US10566526B1
公开(公告)日：2020-02-18
申请号：US16122019
申请日：2018-09-05
Applicant: Allegro MicroSystems, LLC
Inventor： Yen Ting Liu , Maxim Klebanov , Paolo Campiglio , Sundar Chetlur
Abstract: A method includes depositing on a substrate a magnetoresistance stack, depositing a first hard mask on the magnetoresistance stack, depositing a first photoresist on the first hard mask, patterning the first photoresist to expose portions of the first hard mask, and etching the exposed portions of the first hard mask to expose a portion of the magnetoresistance stack. The method further includes stripping the first photoresist, etching the exposed portions of the magnetoresistance stack and the first hard mask to form a first intermediate structure having a base and a pillar structure, depositing an etch barrier on the first intermediate structure, and depositing a second hard mask on the etch barrier. A second photoresist is deposited on the second hard mask. The method further includes patterning the second photoresist to expose portions of the second hard mask, etching the exposed portions of the second hard mask, stripping the second photoresist, etching a portion of the second hard mask, a portion of the etch barrier and the base to form a second intermediate structure, and depositing a capping barrier on the second intermediate structure.
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公开(公告)号：US20240255592A1
公开(公告)日：2024-08-01
申请号：US18161145
申请日：2023-01-30
Applicant: Allegro MicroSystems, LLC
Inventor： Samridh Jaiswal , Paolo Campiglio , Ronald Lehndorff , Yen Ting Liu
CPC classification number: G01R33/091 , G01B7/30 , G01R33/093 , G01R33/096 , G01R33/098
Abstract: In one aspect, a method includes manufacturing a magnetic-field angle sensor on a wafer. The manufacturing includes forming a cosine bridge that includes forming a first magnetoresistance (MR) element. The manufacturing also includes forming a sine bridge that includes forming a second MR element. Forming the first MR element includes using a process to reduce orthogonality errors between the sine bridge and the cosine bridge caused by anisotropy present in magnetic material in the first MR element.
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4.发明公开公开(公告)号：US20240074322A1
公开(公告)日：2024-02-29
申请号：US17823461
申请日：2022-08-30
Applicant: Allegro MicroSystems, LLC
Inventor： Maxim Klebanov , Yen Ting Liu , Sundar Chetlur , Paolo Campiglio , Samridh Jaiswal
CPC classification number: H01L43/12 , G01R33/0052 , H01F41/34 , H01L43/02
Abstract: In one aspect, a method includes depositing magnetoresistance (MR) layers of a MR element on a semiconductor structure; depositing a first hard mask on the MR layers; depositing and patterning a first photoresist on the first hard mask using photolithography to expose portions of the first hard mask; etching the exposed portions of the first hard mask; etching a portion of the MR layers using the first hard mask; depositing a second hard mask on a first capping layer; depositing and patterning a second photoresist on the second hard mask using photolithography to expose portions of the second hard mask; etching the exposed portions of the second hard mask; etching the MR element using the second hard mask; etching portions of the first hard mask down to a top MR layer of the MR element; and depositing a conducting material on the top MR layer to form an electroconductive contact.
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5.发明授权公开(公告)号：US11367830B2
公开(公告)日：2022-06-21
申请号：US17014129
申请日：2020-09-08
Applicant: Allegro MicroSystems, LLC
Inventor： Sundar Chetlur , Maxim Klebanov , Paolo Campiglio , Yen Ting Liu
Abstract: In one aspect, an integrated circuit includes a first conductive layer and a magnetoresistance element (MRE) disposed over and coupled to the first layer through first vias. The MRE is magnetized to produce a first magnetic orientation. The first layer is disposed over and coupled to a second conductive layer in the circuit through second vias. The circuit also includes a metal filler disposed proximate to the MRE. The metal filler is positioned over and coupled to the second layer through third vias. The circuit also includes a thermal dissipation path resulting from a physical input applied to the first MRE. The thermal dissipation path extends through the first through third vias, the first and second layers, an integrated circuit interconnection, and the metal filler.
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Patent Agency Ranking
6.发明公开公开(公告)号：US20230413679A1
公开(公告)日：2023-12-21
申请号：US17804680
申请日：2022-05-31
Applicant: Allegro MicroSystems, LLC
Inventor： Sundar Chetlur , Maxim Klebanov , Yen Ting Liu , Paolo Campiglio
IPC: H01L43/12
CPC classification number: H01L43/12
Abstract: In one aspect, a method includes depositing a capping layer on a semiconductor device structure. The semiconductor device includes a plurality of tunneling magnetoresistance (TMR) elements, a corresponding one hard mask on each TMR element, a metal layer, and a plurality of electroconductive vias directing connecting the TMR elements to the metal layer. The method further includes depositing an insulator on the capping layer, depositing a first photoresist on the insulator, patterning the first photoresist using photolithography to expose portions of the insulator, etching the exposed portions of the insulator and the hard masks to expose top surfaces of the TMR elements, stripping the first photoresist, and depositing a conducting material on the top surfaces of the TMR elements to form an electroconductive contact.
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公开(公告)号：US11005036B2
公开(公告)日：2021-05-11
申请号：US16732679
申请日：2020-01-02
Applicant: Allegro MicroSystems, LLC
Inventor： Yen Ting Liu , Maxim Klebanov , Paolo Campiglio , Sundar Chetlur
Abstract: A magnetoresistance structure includes a base that includes a conductive layer and a first active element on and in direct contact with the conductive layer. The magnetoresistance structure also includes a pillar structure connected to the base. The pillar structure includes a first hard mask, a capping material, a second active element and a tunnel layer. The magnetoresistance structure also further includes an etching barrier deposited on the pillar and the base; a second hard mask deposited on the etching barrier; and a capping barrier deposited on the second hard mask and covering side walls of the base.
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公开(公告)号：US20200075846A1
公开(公告)日：2020-03-05
申请号：US16122019
申请日：2018-09-05
Applicant: Allegro MicroSystems, LLC
Inventor： Yen Ting Liu , Maxim Klebanov , Paolo Campiglio , Sundar Chetlur
Abstract: A method includes depositing on a substrate a magnetoresistance stack, depositing a first hard mask on the magnetoresistance stack, depositing a first photoresist on the first hard mask, patterning the first photoresist to expose portions of the first hard mask, and etching the exposed portions of the first hard mask to expose a portion of the magnetoresistance stack. The method further includes stripping the first photoresist, etching the exposed portions of the magnetoresistance stack and the first hard mask to form a first intermediate structure having a base and a pillar structure, depositing an etch barrier on the first intermediate structure, and depositing a second hard mask on the etch barrier. A second photoresist is deposited on the second hard mask. The method further includes patterning the second photoresist to expose portions of the second hard mask, etching the exposed portions of the second hard mask, stripping the second photoresist, etching a portion of the second hard mask, a portion of the etch barrier and the base to form a second intermediate structure, and depositing a capping barrier on the second intermediate structure.
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公开(公告)号：US20240085463A1
公开(公告)日：2024-03-14
申请号：US17931197
申请日：2022-09-12
Applicant: Allegro MicroSystems, LLC
Inventor： Samridh Jaiswal , Paolo Campiglio , Sundar Chetlur , Maxim Klebanov , Yen Ting Liu
CPC classification number: G01R15/205 , G01R19/0092
Abstract: In one aspect, a sensor includes a first metal layer portion and a second metal layer portion separated by an insulator material; a conductive material layer in electrical contact with the first metal layer portion and the second metal layer portion; and a tunnel magnetoresistance (TMR) element positioned on and in electrical contact with the conductive material layer. A first current is configured to flow from the first metal layer portion, through the conductive material layer, to the second metal layer portion, and a second current is configured to flow from the first metal layer portion, through the conductive material layer, through the TMR element, and exiting through a top of the TMR element.
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公开(公告)号：US20230228828A1
公开(公告)日：2023-07-20
申请号：US17648151
申请日：2022-01-17
Applicant: Allegro MicroSystems, LLC
Inventor： Maxim Klebanov , Yen Ting Liu , Paolo Campiglio , Sundar Chetlur , Harianto Wong
CPC classification number: G01R33/093 , G01R3/00 , G01R33/098
Abstract: In one aspect, a method includes forming a coil in a coil layer, performing planarization on the coil layer, and depositing a magnetoresistance (MR) element on the planarized coil layer. No dielectric material is between the planarized coil layer and the MR element. In another aspect, a magnetic field sensor includes a substrate, a planarized coil layer comprising a coil on the substrate, a magnetoresistance (MR) element in contact with the planarized coil layer, and a capping layer deposited over the MR element and the planarized coil layer. No dielectric material is between the planarized coil layer and the MR element.
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