公开(公告)号：US20250004978A1

公开(公告)日：2025-01-02

申请号：US18537242

申请日：2023-12-12

Applicant: Alpha Networks Inc.

Inventor： Chien-Hua Wang ,  Pao-Kang Mo ,  Shih-Feng Tseng

IPC: G06F13/42

Abstract: A device includes a signal-edge detector, an anomaly detector and a reset-interrupt generator. The signal-edge detector outputs a timing-start signal when detecting that a logic level of an SDA signal from an SDA line of an I2C bus changes from logical high to logical low, and outputs a timing-reset signal when detecting that the logic level changes from logical low to logical high. Upon receiving the timing-start signal, the anomaly detector starts to time a timing duration, and outputs an error signal when the timing duration reaches a preset time duration.
Upon receiving the timing-reset signal, the anomaly detector resets the timing duration to zero. In response to receipt of the error signal, the reset-interrupt generator outputs an interrupt signal to a processor for removing an abnormal state, or outputs a pin-reset signal to an optical module to reset a pin connected to the SDA line.

公开(公告)号：US12130770B2

公开(公告)日：2024-10-29

申请号：US18125483

申请日：2023-03-23

Applicant: Alpha Networks Inc.

Inventor： Pao-Kang Mo ,  Chien-Hua Wang ,  Cheng-Tai Tien ,  Shih-Feng Tseng

IPC: G06F13/42

CPC classification number: G06F13/4291 ,  G06F2213/0016 ,  G06F2213/0026

Abstract: An apparatus for synchronous Ethernet comprises a processor, a field programmable gate array, a synchronizer, a physical layer implementor and a media accessing controller, wherein, the processor transmits a control data through a first transmission interface; the field programmable gate array receives the control data, generates a control instruction in accordance with the control data and transmits the control instruction through a second transmission interface; the synchronizer receives the control instruction and generates a synchronous clock in accordance with the control instruction; and each of the physical layer implementor and the media accessing controller receives and works in accordance with the synchronous clock and media accessing control protocol.