公开(公告)号：US12056067B1

公开(公告)日：2024-08-06

申请号：US17039125

申请日：2020-09-30

Applicant: Amazon Technologies, Inc.

Inventor： Jonathan Cohen ,  Said Bshara ,  Leah Shalev ,  Erez Izenberg ,  Rotem Shaanan

IPC: G06F13/16 ,  G06F9/30 ,  G06F13/28 ,  G06F15/173 ,  G06F15/78

CPC classification number: G06F13/1673 ,  G06F9/30101 ,  G06F13/161 ,  G06F13/1642 ,  G06F13/28 ,  G06F15/17375 ,  G06F15/7807

Abstract: Systems and methods are provided to reduce the latency in accessing an input/output (I/O) hardware register by software executing on a central processing unit (CPU). The hardware register is located in a controller coupled to the CPU via an I/O bus. The CPU software can send a command to the controller for execution. The controller can execute the command and update the hardware register to indicate that the command has been executed. The controller can write contents of the hardware register to a specified address in a CPU memory that is assigned by the CPU software. The CPU software can read the specified address to determine that the command has been executed instead of reading the hardware register on the I/O bus.