公开(公告)号：US11855757B1

公开(公告)日：2023-12-26

申请号：US17643785

申请日：2021-12-10

Applicant: Amazon Technologies, Inc.

Inventor： Julien Ridoux ,  Joshua Benjamin Levinson ,  Said Bshara ,  Erez Izenberg ,  Robert Klein ,  Alan Michael Judge

IPC: G06F1/10 ,  G06F1/12 ,  H04J3/06

CPC classification number: H04J3/0644 ,  G06F1/10 ,  G06F1/12

Abstract: Systems and methods are provided for highly accurate synchronization of machine instances in a distributed, hosted computing environment to a reference timekeeper. In addition to a general communication network accessible to machine instances, the distributed environment includes a second network dedicated to carrying time information, such as a pulse-per-second (PPS) signal to isolated timing hardware within host computing devices. The isolated timing hardware can use the PPS signal, along with a reference time, to set a hardware clock. The isolated timing hardware can further provide an interface to machine instances that enables the instances to read the time of the hardware clock. This configuration enables many instances can share access to a single reference timekeeper, thus synchronizing those instances to a much higher accuracy than in traditional network-based time protocols.

公开(公告)号：US11650835B1

公开(公告)日：2023-05-16

申请号：US16836527

申请日：2020-03-31

Applicant: Amazon Technologies, Inc.

Inventor： Barak Wasserstrom ,  Said Bshara ,  Akram Baransi ,  Omri Itach ,  Tal Zilcer

IPC: G06F9/45 ,  G06F9/455 ,  G06F13/42

CPC classification number: G06F9/455 ,  G06F13/4282 ,  G06F2213/0026

Abstract: Multiple independent endpoint devices can be emulated using a single system on chip (SoC) device. Such a SoC can have multiple cores that can emulate ports according to a specified protocol, such as the peripheral component interconnect express (PCIe) protocol useful for data communications. An emulation agent can manage various aspects of these emulated endpoint devices in software, including serving interrupts for relevant emulated devices according to a determined priority scheme. Interrupts can be registered for each device, and data structures allocated dynamically for a determined number and type(s) of PCIe endpoint devices to be emulated. Each PCIe core on the SoC can function as a separate PCIe endpoint device endpoint for communicating with one or more hosts or other such devices.

公开(公告)号：US09411731B2

公开(公告)日：2016-08-09

申请号：US14829410

申请日：2015-08-18

Applicant: Amazon Technologies, Inc.

Inventor： Adi Habusha ,  Gil Stoler ,  Said Bshara ,  Nafea Bshara

IPC: G06F12/08 ,  G11C7/10

CPC classification number: G06F12/0828 ,  G06F12/0831 ,  G06F12/0833 ,  G06F12/0855 ,  G06F2212/62 ,  G06F2212/621 ,  G11C7/1072

Abstract: A method for writing data, the method may include: receiving or generating, by an interfacing module, a data unit coherent write request for performing a coherent write operation of a data unit to a first address; receiving, by the interfacing module and from a circuit that comprises a cache and a cache controller, a cache coherency indicator that indicates that a most updated version of the content stored at the first address is stored in the cache; and instructing, by the interfacing module, the cache controller to invalidate a cache line of the cache that stored the most updated version of the first address without sending the most updated version of the content stored at the first address from the cache to a memory module that differs from the cache if a length of the data unit equals a length of the cache line.

公开(公告)号：US12093706B2

公开(公告)日：2024-09-17

申请号：US18186748

申请日：2023-03-20

Applicant: Amazon Technologies, Inc.

Inventor： Barak Wasserstrom ,  Said Bshara ,  Akram Baransi ,  Omri Itach ,  Tal Zilcer

IPC: G06F9/455 ,  G06F13/10 ,  G06F13/24 ,  G06F13/42

CPC classification number: G06F9/455 ,  G06F13/105 ,  G06F13/24 ,  G06F13/4221 ,  G06F13/4282 ,  G06F2213/0026

Abstract: Multiple independent endpoint devices can be emulated using a single system on chip (SoC) device. Such a SoC can have multiple cores that can emulate ports according to a specified protocol, such as the peripheral component interconnect express (PCIe) protocol useful for data communications. An emulation agent can manage various aspects of these emulated endpoint devices in software, including serving interrupts for relevant emulated devices according to a determined priority scheme. Interrupts can be registered for each device, and data structures allocated dynamically for a determined number and type(s) of PCIe endpoint devices to be emulated. Each PCIe core on the SoC can function as a separate PCIe endpoint device endpoint for communicating with one or more hosts or other such devices.

公开(公告)号：US12056067B1

公开(公告)日：2024-08-06

申请号：US17039125

申请日：2020-09-30

Applicant: Amazon Technologies, Inc.

Inventor： Jonathan Cohen ,  Said Bshara ,  Leah Shalev ,  Erez Izenberg ,  Rotem Shaanan

IPC: G06F13/16 ,  G06F9/30 ,  G06F13/28 ,  G06F15/173 ,  G06F15/78

CPC classification number: G06F13/1673 ,  G06F9/30101 ,  G06F13/161 ,  G06F13/1642 ,  G06F13/28 ,  G06F15/17375 ,  G06F15/7807

Abstract: Systems and methods are provided to reduce the latency in accessing an input/output (I/O) hardware register by software executing on a central processing unit (CPU). The hardware register is located in a controller coupled to the CPU via an I/O bus. The CPU software can send a command to the controller for execution. The controller can execute the command and update the hardware register to indicate that the command has been executed. The controller can write contents of the hardware register to a specified address in a CPU memory that is assigned by the CPU software. The CPU software can read the specified address to determine that the command has been executed instead of reading the hardware register on the I/O bus.

公开(公告)号：US11086801B1

公开(公告)日：2021-08-10

申请号：US15099188

申请日：2016-04-14

Applicant: Amazon Technologies, Inc.

Inventor： Georgy Machulsky ,  Nafea Bshara ,  Netanel Israel Belgazal ,  Evgeny Schmeilin ,  Said Bshara ,  Alexander Matushevsky

IPC: G06F13/16 ,  G06F13/40 ,  G06F13/42 ,  G06F13/28 ,  G06F3/06 ,  G06F9/455

Abstract: A resource request is received by a network device from a virtual machine running on a host. The resource request includes a requested resource size. The network device allocates resources of the network device in response to the resource request. A resource response is sent by the network device to the virtual machine that generated the resource request. The resource response includes a location of the allocated resource.

公开(公告)号：US10951537B1

公开(公告)日：2021-03-16

申请号：US16143217

申请日：2018-09-26

Applicant: Amazon Technologies, Inc.

Inventor： Said Bshara ,  Clint Joseph Sbisa

IPC: H04L12/70 ,  H04L12/863 ,  H04L12/835

Abstract: A network device, such as a Network Interface Card (NIC), can have a receive queue (RxQ) that changes size based on whether the network device is in a normal operating mode or in a maintenance mode. In a normal operating mode, it is desirable that the receive queue has a smaller number of free buffers, to increase cache locality in a processor subsystem. However, there can be known periods when the receive queue can be overloaded. During a maintenance period, it is desirable that the receive queue absorbs a large burst of network packets while the processor subsystem is not processing the packets. A solution is to maintain a receive queue at a smaller percentage of its maximum during the normal operation mode, but then before or upon entering the maintenance mode, expand the receive queue to a larger size.

公开(公告)号：US10754797B1

公开(公告)日：2020-08-25

申请号：US16256666

申请日：2019-01-24

Applicant: Amazon Technologies, Inc.

Inventor： Georgy Machulsky ,  Netanel Israel Belgazal ,  Said Bshara ,  Nafea Bshara ,  Adi Habusha

IPC: G06F13/16 ,  G06F13/42 ,  G06F13/24 ,  G06F13/28 ,  G06F13/40 ,  G06F9/455

Abstract: A network device stores information associated with a packet in a queue. The network device sends an interrupt to a host to notify the host of completion of processing the packet. A Memory-Mapped Input/Output (MMIO) write transaction is received that includes a pointer update associated with the queue and an interrupt unmasking value. The pointer is updated and the interrupt is unmasked based on receiving the single MMIO write transaction.

公开(公告)号：US10409744B1

公开(公告)日：2019-09-10

申请号：US15251877

申请日：2016-08-30

Applicant: Amazon Technologies, Inc.

Inventor： Saar Gross ,  Said Bshara ,  Adi Habusha ,  Nafea Bshara ,  Ronen Shitrit

IPC: G06F1/32 ,  G06F13/24 ,  G06F13/42 ,  G06F1/3287 ,  G06F1/3206 ,  G06F1/3296 ,  G06F1/3293

Abstract: A processor in a peripheral device can include a wait-for-event mechanism, through which the processor can enter low-power mode and be woken from lower-power mode with an event. Using an event, rather than an interrupt, allows the processor to wake without the latency incurred by an interrupt handling routine. In various implementations, the processor may be configured to execute a sequence of instructions that include a wait-for-event instruction. The wait-for-event instruction can be called when the processor is idle. The wait-for-event instruction may initiate a low-power mode for the processor, wherein the processor suspends executing the sequence of instructions. The processor may further be configured to receive, at an event input, an event signal. The event signal may cause the processor to exit the low-power mode and to resume executing the sequence of instructions from the point at which the processor suspended executing the sequence of instructions.

公开(公告)号：US12026103B1

公开(公告)日：2024-07-02

申请号：US17444352

申请日：2021-08-03

Applicant: Amazon Technologies, Inc.

Inventor： Georgy Machulsky ,  Nafea Bshara ,  Netanel Israel Belgazal ,  Evgeny Schmeilin ,  Said Bshara ,  Alexander Matushevsky

IPC: G06F13/00 ,  G06F3/06 ,  G06F9/455 ,  G06F13/16 ,  G06F13/28 ,  G06F13/40 ,  G06F13/42

CPC classification number: G06F13/16 ,  G06F3/0604 ,  G06F3/0631 ,  G06F3/067 ,  G06F9/45558 ,  G06F13/28 ,  G06F13/4068 ,  G06F13/4282 ,  G06F2009/45583 ,  G06F2009/45595

Abstract: A resource request is received by a peripheral device from host processing logic. The resource request includes a requested resource size. The peripheral device allocates resource of the peripheral device in response to the resource request. A resource response is sent by the peripheral device to the host processing logic. The resource response includes a location of the allocated resource.