公开(公告)号：US11467760B1

公开(公告)日：2022-10-11

申请号：US17247242

申请日：2020-12-04

Applicant: Amazon Technologies, Inc.

Inventor： Itai Avron ,  Erez Sabbag ,  Anna Rom-Saksonov

IPC: G06F3/06 ,  G06F11/10 ,  H03M13/29

Abstract: Systems, apparatuses, and corresponding techniques are described for selective erasure decoding on memory devices. Erasure decoding is performed on error correction codes (ECCs) read from memory locations associated with errors that are correctable through erasure decoding, as indicated by erasure information available to a memory controller or other device configured to decode ECCs. The erasure information can indicate locations within individual memory devices and, optionally, at different memory hierarchy levels. When the erasure information indicates that a location being read from is not associated with an error that is correctable through erasure decoding, regular error decoding is performed on ECCs read from such locations. Selective erasure decoding can be performed in connection with separate read operations that access different memory devices or a single read operation that accesses multiple memory devices concurrently.

公开(公告)号：US12175285B1

公开(公告)日：2024-12-24

申请号：US17305151

申请日：2021-06-30

Applicant: Amazon Technologies, Inc.

Inventor： Nitzan Zisman ,  Said Bshara ,  Erez Izenberg ,  Avigdor Segal ,  Jonathan Cohen ,  Anna Rom-Saksonov ,  Leah Shalev ,  Shadi Ammouri

IPC: G06F9/48 ,  G06F9/30 ,  G06F9/355 ,  G06F9/50 ,  G06F13/28

Abstract: An integrated circuit for distributing processing tasks includes a pre-selector circuit and a scheduler circuit. The pre-selector circuit is configured to receive a processing task, determine a category of the processing task, and select, from a set of task distribution techniques and based at least in part on the category of the processing task, a task distribution technique for distributing the processing task to a group of processing units. The scheduler circuit is configured to implement the selected task distribution technique to select, from the group of processing units, a target processing unit for performing the processing task.

公开(公告)号：US11386008B1

公开(公告)日：2022-07-12

申请号：US17018105

申请日：2020-09-11

Applicant: Amazon Technologies, inc.

Inventor： Anna Rom-Saksonov ,  Erez Izenberg ,  Avigdor Segal ,  Jonathan Cohen ,  Nitzan Zisman ,  Noam Attias

IPC: G06F12/0846 ,  G06F12/02 ,  G06F11/10 ,  G06F11/07 ,  G11C15/00 ,  G11C15/04

Abstract: A memory apparatus for detecting false hits in a content-addressable memory (CAM) is disclosed. The memory apparatus includes a controller coupled to the CAM and a memory. The controller receives a search result including an address from the CAM, the address corresponding to a matching entry from a first set of data entries that matches a search tag. The controller provides a read address based on the address to the memory, which returns a second data entry from a second set of data entries corresponding to the read address. The controller receives the read data and generates an error detection result based on a comparison between the second data entry and the search tag.