公开(公告)号：US10955472B1

公开(公告)日：2021-03-23

申请号：US16444917

申请日：2019-06-18

Applicant: Amazon Technologies, Inc.

Inventor： Dan Trock ,  Valentin Bader ,  Shlomi Vilozny ,  Shimon Rahamim ,  Danny Sapoznikov ,  Yair Armoza ,  Itai Avron

IPC: G01R31/3177 ,  G01R31/317

Abstract: An integrated circuit includes first and second cores. Each core has a power-switchable portion in a first power domain in which an operating power is turned on or off in response to a power control signal. The first power domain includes a first scan chain, and the first power domain also includes a plurality of outputs. Each core also includes an always-on portion in a second power domain in which the operating power is maintained during testing of the integrated circuit. The second power domain also has a second scan chain. The second power domain further includes respective isolation gates coupled to the plurality of outputs of the first power domain, and the second scan chain includes a respective wrapper cell coupled to some isolation gates. The integrated circuit is configured to power off and isolate the power-switchable portion in the first power domain based on a scan test result.

公开(公告)号：US09934184B1

公开(公告)日：2018-04-03

申请号：US14865431

申请日：2015-09-25

Applicant: Amazon Technologies, Inc.

Inventor： Guy Nakibly ,  Adi Habusha ,  Nafea Bshara ,  Itai Avron

IPC: G06F13/00 ,  G06F3/00 ,  G06F13/40 ,  G06F13/364 ,  G06F13/42 ,  G06F13/16

CPC classification number: G06F13/4054 ,  G06F13/1626 ,  G06F13/364 ,  G06F13/4282

Abstract: Provided are systems and methods for distributing ordering tasks in a computing system that includes master and target devices. In some implementations, a computing device is provided. The computing device may include a master device that is operable to initiate transactions. The computing device may further include a target device that is operable to receive transactions. In some implementations, the master device may be configured to transmit one or more transactions to the target device. The master device may further asynchronously indicate to the target device a number of transactions to execute. The master device may further asynchronously receive from the target device a number of transactions executed. The master device may then signal that at least one transaction from the one or more transactions it sent has completed.

公开(公告)号：US11909850B1

公开(公告)日：2024-02-20

申请号：US17304593

申请日：2021-06-23

Applicant: Amazon Technologies, Inc.

Inventor： Gal Kochavi ,  Itai Avron ,  Benny Pollak

IPC: H04L69/18 ,  H04L1/00 ,  H04L43/18

CPC classification number: H04L69/18 ,  H04L1/001 ,  H04L1/0018 ,  H04L43/18 ,  H04L2212/00

Abstract: Systems and methods are provided to improve a communication channel dynamically and autonomously based on the status of the communication traffic on the communication channel between a first integrated circuit (IC) and a second IC. The communication traffic on the communication channel can be monitored, and latency, bandwidth, link quality, or power consumption associated with the communication channel for the monitored communication traffic can be determined dynamically. A modified protocol for the communication channel that can improve the communication channel as compared to an existing protocol can be determined based on the information related to the latency, bandwidth, link quality, or the power consumption. The existing protocol can be changed autonomously to the modified protocol as the communication traffic varies.

公开(公告)号：US10733048B1

公开(公告)日：2020-08-04

申请号：US16219493

申请日：2018-12-13

Applicant: Amazon Technologies, Inc.

Inventor： Itai Avron ,  Adi Habusha ,  Gal Paikin ,  Simaan Bahouth

IPC: H03M13/00 ,  G06F11/10 ,  H03M13/09 ,  H03M13/15 ,  G11C29/42 ,  G11C29/52 ,  G06F12/14

Abstract: A method and circuit are disclosed to calculate an error correction code (ECC) and perform a decryption in parallel when reading memory data. There are multiple modes of operation. In a normal parallel mode of operation, the data passes through a decryption engine. Simultaneously, the same data passes through an ECC decode engine. However, if no error is detected, the output of the decode engine is discarded. If there is an ECC error, an error indication is made so that the corresponding data exiting the decryption engine is discarded. The circuit then switches to a serial mode of operation, wherein the ECC decode engine corrects the data and resends the corrected data again through the decryption engine. The circuit is maintained in the serial mode until a decision is made to switch back to the parallel mode, such as when a pipeline of the ECC engine becomes empty.

公开(公告)号：US12164445B1

公开(公告)日：2024-12-10

申请号：US17592233

申请日：2022-02-03

Applicant: Amazon Technologies, Inc.

Inventor： Ofer Naaman ,  Itai Avron ,  Adi Habusha ,  Aviv Bakal ,  Leonid Froenchenko

IPC: G06F13/00 ,  G06F13/16

Abstract: The coherency of data can be maintained even for accelerators that may not directly support, or be part of, a coherency protocol or domain. A pair of agents can be utilized that include an application accelerator agent and a coherent agent. The coherent agent can support the coherency protocol and track coherency information for data in the coherency environment, to ensure coherent access to the data. The application accelerator agent can work with the coherent agent to obtain the data according to the coherency protocol, then perform operations on the data corresponding to a respective application or process. Such an approach enables an accelerator to function like a processor or processor core that otherwise supports the coherency protocol and is part of the coherency domain. A single coherent agent can be used to maintain coherency information for multiple other components or agents.

公开(公告)号：US11996859B1

公开(公告)日：2024-05-28

申请号：US17119572

申请日：2020-12-11

Applicant: Amazon Technologies, Inc.

Inventor： Itai Avron ,  Erez Sabbag

IPC: H03M13/11 ,  G11C29/36 ,  G11C29/42 ,  H03M13/15 ,  G06F11/10 ,  G11C13/00 ,  G11C29/02 ,  G11C29/44 ,  G11C29/52

CPC classification number: H03M13/1105 ,  G11C29/36 ,  G11C29/42 ,  H03M13/1515 ,  H03M13/152 ,  G06F11/1048 ,  G11C2013/0057 ,  G11C29/024 ,  G11C2029/3602 ,  G11C29/44 ,  G11C29/52

Abstract: A decoder is disclosed with error correction for memory data. The decoder's error correction is extended to additional faulty bits by integrating a memory test into the error correction to identify faulty bits in the memory data. A method for correction can include writing a known pattern to the failing address (and possibly to neighboring addresses), reading the known pattern back and comparing the read data to the written pattern to identify the failing bits. The failing bits are then used together with the error correction data to correct memory data having multiple incorrect bits or to alert other components about the failing bit locations.

公开(公告)号：US11809349B1

公开(公告)日：2023-11-07

申请号：US17304240

申请日：2021-06-16

Applicant: Amazon Technologies, Inc.

Inventor： Ali Ghassan Saidi ,  Adi Habusha ,  Itai Avron ,  Tzachi Zidenberg ,  Ofer Naaman

IPC: G06F13/24 ,  G06F11/07 ,  G06F9/455

CPC classification number: G06F13/24 ,  G06F9/45558 ,  G06F11/0712 ,  G06F2009/45579 ,  G06F2201/815 ,  G06F2213/24

Abstract: An interposer circuit is used between an interrupt controller and a processor core to facilitate direct injection of a virtual interrupt into a guest executing on the processor core, even though the interrupt controller does not support the direct injection. The interposer circuit can convert a command received from the interrupt controller for a physical interrupt into another command for a virtual interrupt to make the processor core believe that the processor core has received a virtual interrupt even though the interrupt controller is not able to provide the virtual interrupt. The virtual interrupt can be directly injected into the processor core without the intervention of a hypervisor executing on the processor core.

公开(公告)号：US11768630B1

公开(公告)日：2023-09-26

申请号：US17452548

申请日：2021-10-27

Applicant: Amazon Technologies, Inc.

Inventor： Itai Avron ,  Anat Arbely

IPC: G06F3/06 ,  G06F13/16

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0679 ,  G06F13/1668

Abstract: A memory controller can receive transactions from an interconnect to access the memory. The memory controller can use a credit-based scheme to request the interconnect to send specific memory transactions that can be scheduled in a desirable order using a credit type associated with each transaction. In some embodiments, the memory controller can keep track of the number of transactions directed to each bank of the memory based on a credit type, so that specific transactions directed towards the underutilized banks can be requested and scheduled in a manner to utilize all the banks more uniformly to improve the system performance.

公开(公告)号：US11467760B1

公开(公告)日：2022-10-11

申请号：US17247242

申请日：2020-12-04

Applicant: Amazon Technologies, Inc.

Inventor： Itai Avron ,  Erez Sabbag ,  Anna Rom-Saksonov

IPC: G06F3/06 ,  G06F11/10 ,  H03M13/29

Abstract: Systems, apparatuses, and corresponding techniques are described for selective erasure decoding on memory devices. Erasure decoding is performed on error correction codes (ECCs) read from memory locations associated with errors that are correctable through erasure decoding, as indicated by erasure information available to a memory controller or other device configured to decode ECCs. The erasure information can indicate locations within individual memory devices and, optionally, at different memory hierarchy levels. When the erasure information indicates that a location being read from is not associated with an error that is correctable through erasure decoding, regular error decoding is performed on ECCs read from such locations. Selective erasure decoding can be performed in connection with separate read operations that access different memory devices or a single read operation that accesses multiple memory devices concurrently.

公开(公告)号：US10255213B1

公开(公告)日：2019-04-09

申请号：US15083113

申请日：2016-03-28

Applicant: Amazon Technologies, Inc.

Inventor： Adi Habusha ,  Itai Avron ,  Yaakov Gendel

IPC: G06F13/38 ,  G06F13/40 ,  G06F5/10 ,  G06F3/06

Abstract: Provided are methods and adapter devices for buffering write transactions directed to a large space. In various implementations, an adapter device may include a sequential address buffer and a memory. A region of the memory may be configured as a data block, which may be associated with an address range. The address range may correspond to a region of an address space of a target device. The adapter device may be configured to receive a write transaction, the write transaction having an address and data. The adapter device may further write the address to the sequential address buffer. The adapter device may further determine that the address is within the address range, and to write the data to the data block. The adapter device may further, upon the occurrence of an event, write the data from the data block to the region of the address space of the target device.