公开(公告)号：US11726665B1

公开(公告)日：2023-08-15

申请号：US17305044

申请日：2021-06-29

Applicant: Amazon Technologies, Inc.

Inventor： Erez Sabbag ,  Itai Avron

IPC: G06F3/06

CPC classification number: G06F3/0619 ,  G06F3/0652 ,  G06F3/0655 ,  G06F3/0679

Abstract: Techniques for encoding additional data in a memory without requiring an increase to the physical storage capacity of the memory device are described. Additional data can be encoded with error correction code symbols without having to physically store the additional data in memory, while retaining the number of error correction code bits used by the memory. When data is read from memory without the additional data, erasure decoding can be performed to recover the additional data. When errors are encountered in the data read from memory, the errors can be treated as erasures for different predictions of the error locations to determine if the errors can be corrected.

公开(公告)号：US11645075B1

公开(公告)日：2023-05-09

申请号：US17305152

申请日：2021-06-30

Applicant: Amazon Technologies, Inc.

Inventor： Barak Wasserstrom ,  Adi Habusha ,  Ron Diamant ,  Erez Sabbag

IPC: G06F9/30 ,  G06F9/455 ,  G06N3/08 ,  G06K9/62 ,  G06F9/38

CPC classification number: G06F9/30058 ,  G06F9/3836 ,  G06F9/45558 ,  G06K9/6256 ,  G06N3/08

Abstract: Execution flows of a program can be characterized by a series of execution events. The rates at which these execution events occur for a particular program can be collected periodically, and the execution events statistics can be utilized for both training a machine learning model, and later on for making classification inferences to determine whether a program run contains any abnormality. When an abnormality is encountered, an alert can be generated and provided to supervisory logic of a computing system to indicate that an abnormal program flow has been detected.

公开(公告)号：US11606104B1

公开(公告)日：2023-03-14

申请号：US17545846

申请日：2021-12-08

Applicant: Amazon Technologies, Inc.

Inventor： Avigdor Segal ,  Leonid Baryudin ,  Erez Izenberg ,  Erez Sabbag ,  Se Wang Oh ,  Noga Smith

IPC: G06F11/00 ,  H03M13/09 ,  G06F11/14

Abstract: The integrity of transmitted data can be protected by causing that data to be transmitted twice, and calculating protection information (PI) for the data from each transmission. The PI can include information such as a checksum or signature that should have the same value if the data from each transmission is the same. If the PI values are not the same, an error handling procedure can be activated, such as may retry the transmission. For write operations, the data can be transmitted twice from a source to a storage destination, while for read operations, the data can be transmitted to a recipient then sent back from the recipient to the storage device, with PI calculated for each transmission. A component such as a storage processor can perform at least this comparison step. Such approaches can also be used for network transmission or high performance computing.

公开(公告)号：US11996859B1

公开(公告)日：2024-05-28

申请号：US17119572

申请日：2020-12-11

Applicant: Amazon Technologies, Inc.

Inventor： Itai Avron ,  Erez Sabbag

IPC: H03M13/11 ,  G11C29/36 ,  G11C29/42 ,  H03M13/15 ,  G06F11/10 ,  G11C13/00 ,  G11C29/02 ,  G11C29/44 ,  G11C29/52

CPC classification number: H03M13/1105 ,  G11C29/36 ,  G11C29/42 ,  H03M13/1515 ,  H03M13/152 ,  G06F11/1048 ,  G11C2013/0057 ,  G11C29/024 ,  G11C2029/3602 ,  G11C29/44 ,  G11C29/52

Abstract: A decoder is disclosed with error correction for memory data. The decoder's error correction is extended to additional faulty bits by integrating a memory test into the error correction to identify faulty bits in the memory data. A method for correction can include writing a known pattern to the failing address (and possibly to neighboring addresses), reading the known pattern back and comparing the read data to the written pattern to identify the failing bits. The failing bits are then used together with the error correction data to correct memory data having multiple incorrect bits or to alert other components about the failing bit locations.

公开(公告)号：US11467760B1

公开(公告)日：2022-10-11

申请号：US17247242

申请日：2020-12-04

Applicant: Amazon Technologies, Inc.

Inventor： Itai Avron ,  Erez Sabbag ,  Anna Rom-Saksonov

IPC: G06F3/06 ,  G06F11/10 ,  H03M13/29

Abstract: Systems, apparatuses, and corresponding techniques are described for selective erasure decoding on memory devices. Erasure decoding is performed on error correction codes (ECCs) read from memory locations associated with errors that are correctable through erasure decoding, as indicated by erasure information available to a memory controller or other device configured to decode ECCs. The erasure information can indicate locations within individual memory devices and, optionally, at different memory hierarchy levels. When the erasure information indicates that a location being read from is not associated with an error that is correctable through erasure decoding, regular error decoding is performed on ECCs read from such locations. Selective erasure decoding can be performed in connection with separate read operations that access different memory devices or a single read operation that accesses multiple memory devices concurrently.