SYMMETRIC COMMUNICATION FOR ASYMMETRIC ENVIRONMENTS

    公开(公告)号:US20240171662A1

    公开(公告)日:2024-05-23

    申请号:US18427670

    申请日:2024-01-30

    CPC classification number: H04L69/22 H04L67/14

    Abstract: Communication in an asymmetric multiengine system is handled using engine routing tables defining subsets of engines to control engine-to-engine connection mapping. Local devices perform an engine selection process that includes selecting an engine routing table based on a number of remote engines in a remote device and selecting an engine set from the selected table based on an identifier of the remote device. A connection to the remote device is created using the engines identified in the selected engine set.

    Data integrity protection
    5.
    发明授权

    公开(公告)号:US11606104B1

    公开(公告)日:2023-03-14

    申请号:US17545846

    申请日:2021-12-08

    Abstract: The integrity of transmitted data can be protected by causing that data to be transmitted twice, and calculating protection information (PI) for the data from each transmission. The PI can include information such as a checksum or signature that should have the same value if the data from each transmission is the same. If the PI values are not the same, an error handling procedure can be activated, such as may retry the transmission. For write operations, the data can be transmitted twice from a source to a storage destination, while for read operations, the data can be transmitted to a recipient then sent back from the recipient to the storage device, with PI calculated for each transmission. A component such as a storage processor can perform at least this comparison step. Such approaches can also be used for network transmission or high performance computing.

    Low-latency packet processing for network device

    公开(公告)号:US11467998B1

    公开(公告)日:2022-10-11

    申请号:US17203231

    申请日:2021-03-16

    Abstract: Techniques for low-latency packet processing are disclosed. A network device receives a first set of write transactions including a first set of data segments corresponding to a first DMA descriptor from a host. The network device receives a second set of write transactions including a second set of data segments corresponding to a second DMA descriptor from the host. The network device detects that the first set of data segments have been written. In response to detecting that the first set of data segments have been written, and prior to completely writing the second set of data segments and to receiving a packet notifier from the host, the network device processes the first DMA descriptor.

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