公开(公告)号：US10990445B2

公开(公告)日：2021-04-27

申请号：US15669445

申请日：2017-08-04

Applicant: Apple Inc.

Inventor： Mark D. Earl ,  Dimitri Tan ,  Christopher L. Spencer ,  Jeffrey T. Brady ,  Ralph C. Taylor ,  Terence M. Potter

IPC: G06F9/50 ,  G06F9/38

Abstract: In various embodiments, a resource allocation management circuit may allocate a plurality of different types of hardware resources (e.g., different types of registers) to a plurality of threads. The different types of hardware resources may correspond to a plurality of hardware resource allocation circuits. The resource allocation management circuit may track allocation of the hardware resources to the threads using state identification values of the threads. In response to determining that fewer than a respective requested number of one or more types of the hardware resources are available, the resource allocation management circuit may identify one or more threads for deallocation. As a result, the hardware resource allocation system may allocate hardware resources to threads more efficiently (e.g., may deallocate hardware resources allocated to fewer threads), as compared to a hardware resource allocation system that does not track allocation of hardware resources to threads using state identification values.

公开(公告)号：US20210248006A1

公开(公告)日：2021-08-12

申请号：US17240406

申请日：2021-04-26

Applicant: Apple Inc.

Inventor： Mark D. Earl ,  Dimitri Tan ,  Christopher L. Spencer ,  Jeffrey T. Brady ,  Ralph C. Taylor ,  Terence M. Potter

IPC: G06F9/50

Abstract: In various embodiments, a resource allocation management circuit may allocate a plurality of different types of hardware resources (e.g., different types of registers) to a plurality of threads. The different types of hardware resources may correspond to a plurality of hardware resource allocation circuits. The resource allocation management circuit may track allocation of the hardware resources to the threads using state identification values of the threads. In response to determining that fewer than a respective requested number of one or more types of the hardware resources are available, the resource allocation management circuit may identify one or more threads for deallocation. As a result, the hardware resource allocation system may allocate hardware resources to threads more efficiently (e.g., may deallocate hardware resources allocated to fewer threads), as compared to a hardware resource allocation system that does not track allocation of hardware resources to threads using state identification values.

公开(公告)号：US20250068564A1

公开(公告)日：2025-02-27

申请号：US18583520

申请日：2024-02-21

Applicant: Apple Inc.

Inventor： Dimitri Tan ,  William V. Miller

IPC: G06F12/084 ,  G06F12/0811 ,  G06T1/60

Abstract: In disclosed embodiment, a graphics processor is configured to operate on data in multiple memory spaces. Data cache circuitry may cache data for the graphics processor circuitry, including data from multiple memory spaces. The data cache circuitry may include tag circuitry configured to compare the following information from access requests to the data cache circuitry with tags of entries in the data cache circuitry: memory space information and a tag portion of a requested address. The tag portion of a requested address may be different (e.g., a different set of bit indices within the address) for at least two of the multiple memory spaces. Disclosed techniques may advantageously facilitate caching for disparate clients with different cache line sizes, address spaces, etc., e.g., in unified memory architectures.

公开(公告)号：US10699368B1

公开(公告)日：2020-06-30

申请号：US15690954

申请日：2017-08-30

Applicant: Apple Inc.

Inventor： Christopher L. Spencer ,  Terence M. Potter ,  Dimitri Tan

IPC: G06T1/60 ,  G06T15/80 ,  G06T15/00 ,  G06T1/20 ,  G06F12/02

Abstract: Techniques are disclosed relating to memory allocation in a graphics shader. In some embodiments, a memory for storing input data for operations by the shader is shared for multiple different types of tasks (e.g., pixel shading tasks and compute tasks). In some embodiments, a graphics device is configured to separately process different portions (e.g., tiles) of a frame of graphics data. In some embodiments, the graphics device is configured to dynamically adjust the number of frame portions processed in parallel based on allocation information, where the allocation information is determined based on requests for other types of tasks. This may prevent pixel shading tasks from stalling other tasks for extended periods and may allow dynamic adjustments memory allocation mid-render.

公开(公告)号：US10698687B1

公开(公告)日：2020-06-30

申请号：US15695263

申请日：2017-09-05

Applicant: Apple Inc.

Inventor： Dimitri Tan ,  Jeffrey T. Brady ,  Terence M. Potter ,  Jeffrey M. Broton ,  Frank W. Liljeros

IPC: G06F13/22 ,  G06F9/30 ,  G06F9/38 ,  G06F9/46

Abstract: An example system includes a plurality of execution units, a shared resource, and an allocation control circuit. Each execution unit may generate a resource allocation request that includes a resource allocation size. The allocation control circuit may select a particular resource allocation request from the plurality of resource allocation requests, and determine an availability, based on an allocation register, of contiguous resource blocks within the shared resource. In response to determining that a number of the contiguous resource blocks satisfies a requested allocation size, the allocation control circuit may select an address corresponding to a particular resource block of the one or more contiguous resource blocks, and allocate the resource blocks to a corresponding execution unit. In response to a beginning of a second system clock cycle, the allocation control circuit may also update the allocation register based on the selected address and the requested allocation size.

公开(公告)号：US20190042312A1

公开(公告)日：2019-02-07

申请号：US15669445

申请日：2017-08-04

Applicant: Apple Inc.

Inventor： Mark D. Earl ,  Dimitri Tan ,  Christopher L. Spencer ,  Jeffrey T. Brady ,  Ralph C. Taylor ,  Terence M. Potter

IPC: G06F9/50

Abstract: In various embodiments, a resource allocation management circuit may allocate a plurality of different types of hardware resources (e.g., different types of registers) to a plurality of threads. The different types of hardware resources may correspond to a plurality of hardware resource allocation circuits. The resource allocation management circuit may track allocation of the hardware resources to the threads using state identification values of the threads. In response to determining that fewer than a respective requested number of one or more types of the hardware resources are available, the resource allocation management circuit may identify one or more threads for deallocation. As a result, the hardware resource allocation system may allocate hardware resources to threads more efficiently (e.g., may deallocate hardware resources allocated to fewer threads), as compared to a hardware resource allocation system that does not track allocation of hardware resources to threads using state identification values.