公开(公告)号：US20210248006A1

公开(公告)日：2021-08-12

申请号：US17240406

申请日：2021-04-26

Applicant: Apple Inc.

Inventor： Mark D. Earl ,  Dimitri Tan ,  Christopher L. Spencer ,  Jeffrey T. Brady ,  Ralph C. Taylor ,  Terence M. Potter

IPC: G06F9/50

Abstract: In various embodiments, a resource allocation management circuit may allocate a plurality of different types of hardware resources (e.g., different types of registers) to a plurality of threads. The different types of hardware resources may correspond to a plurality of hardware resource allocation circuits. The resource allocation management circuit may track allocation of the hardware resources to the threads using state identification values of the threads. In response to determining that fewer than a respective requested number of one or more types of the hardware resources are available, the resource allocation management circuit may identify one or more threads for deallocation. As a result, the hardware resource allocation system may allocate hardware resources to threads more efficiently (e.g., may deallocate hardware resources allocated to fewer threads), as compared to a hardware resource allocation system that does not track allocation of hardware resources to threads using state identification values.

公开(公告)号：US10990445B2

公开(公告)日：2021-04-27

申请号：US15669445

申请日：2017-08-04

Applicant: Apple Inc.

Inventor： Mark D. Earl ,  Dimitri Tan ,  Christopher L. Spencer ,  Jeffrey T. Brady ,  Ralph C. Taylor ,  Terence M. Potter

IPC: G06F9/50 ,  G06F9/38

Abstract: In various embodiments, a resource allocation management circuit may allocate a plurality of different types of hardware resources (e.g., different types of registers) to a plurality of threads. The different types of hardware resources may correspond to a plurality of hardware resource allocation circuits. The resource allocation management circuit may track allocation of the hardware resources to the threads using state identification values of the threads. In response to determining that fewer than a respective requested number of one or more types of the hardware resources are available, the resource allocation management circuit may identify one or more threads for deallocation. As a result, the hardware resource allocation system may allocate hardware resources to threads more efficiently (e.g., may deallocate hardware resources allocated to fewer threads), as compared to a hardware resource allocation system that does not track allocation of hardware resources to threads using state identification values.

公开(公告)号：US20190244323A1

公开(公告)日：2019-08-08

申请号：US15887547

申请日：2018-02-02

Applicant: Apple Inc.

Inventor： Benjiman L. Goodman ,  Christopher L. Spencer ,  Mark D. Earl ,  Robert S. Hartog ,  Timothy M. Kelley

IPC: G06T1/20 ,  G06F9/30 ,  G06F9/38

CPC classification number: G06T1/20 ,  G06F9/30101 ,  G06F9/3867

Abstract: Techniques are disclosed relating to processing groups of graphics work (which may be referred to as “kicks”) using a graphics processing pipeline. In some embodiments, a graphics processor includes multiple sets of configuration registers such that multiple kicks can be processed in the pipeline at the same time. In some embodiments, kicks are pipelined such that a subsequent kick ramps up use of hardware resources as a previous kick winds down. In some embodiments, the graphics processing may execute kicks concurrently and/or preemptively, e.g., based on a priority scheme. In some embodiments, the disclosed techniques may be used with pipelines that include front and back-end fixed function circuitry as well as shared programmable resources such as shader cores. In various embodiments, the disclosed techniques may improve overall performance and/or reduce latency for high-priority graphics tasks.

公开(公告)号：US20190042312A1

公开(公告)日：2019-02-07

申请号：US15669445

申请日：2017-08-04

Applicant: Apple Inc.

Inventor： Mark D. Earl ,  Dimitri Tan ,  Christopher L. Spencer ,  Jeffrey T. Brady ,  Ralph C. Taylor ,  Terence M. Potter

IPC: G06F9/50

Abstract: In various embodiments, a resource allocation management circuit may allocate a plurality of different types of hardware resources (e.g., different types of registers) to a plurality of threads. The different types of hardware resources may correspond to a plurality of hardware resource allocation circuits. The resource allocation management circuit may track allocation of the hardware resources to the threads using state identification values of the threads. In response to determining that fewer than a respective requested number of one or more types of the hardware resources are available, the resource allocation management circuit may identify one or more threads for deallocation. As a result, the hardware resource allocation system may allocate hardware resources to threads more efficiently (e.g., may deallocate hardware resources allocated to fewer threads), as compared to a hardware resource allocation system that does not track allocation of hardware resources to threads using state identification values.

公开(公告)号：US10699368B1

公开(公告)日：2020-06-30

申请号：US15690954

申请日：2017-08-30

Applicant: Apple Inc.

Inventor： Christopher L. Spencer ,  Terence M. Potter ,  Dimitri Tan

IPC: G06T1/60 ,  G06T15/80 ,  G06T15/00 ,  G06T1/20 ,  G06F12/02

Abstract: Techniques are disclosed relating to memory allocation in a graphics shader. In some embodiments, a memory for storing input data for operations by the shader is shared for multiple different types of tasks (e.g., pixel shading tasks and compute tasks). In some embodiments, a graphics device is configured to separately process different portions (e.g., tiles) of a frame of graphics data. In some embodiments, the graphics device is configured to dynamically adjust the number of frame portions processed in parallel based on allocation information, where the allocation information is determined based on requests for other types of tasks. This may prevent pixel shading tasks from stalling other tasks for extended periods and may allow dynamic adjustments memory allocation mid-render.

公开(公告)号：US10074210B1

公开(公告)日：2018-09-11

申请号：US15659188

申请日：2017-07-25

Applicant: Apple Inc.

Inventor： Christopher L. Spencer ,  Karl D. Mann ,  Ralph C. Taylor ,  Dinesh D. Kuwar

IPC: G06T15/50 ,  G06T15/60 ,  G06T15/40 ,  G06T15/00 ,  G06T15/08 ,  G06T15/80 ,  G06T17/20 ,  G09G5/00

CPC classification number: G06T15/40 ,  G06T11/40 ,  G06T15/005 ,  G06T15/08 ,  G06T15/80 ,  G06T17/20 ,  G09G5/00 ,  G09G5/363

Abstract: Techniques are disclosed relating to rendering graphics objects that require shader operations to determine visibility. In some embodiments, a graphics unit is configured to process feedback objects, which may require shading to determine whether they are visible relative to previously-processed objects, out of draw order. For example, in embodiments where a buffer is used to store fragment data for deferred rendering, the graphics unit may bypass the buffer and shade feedback objects ahead of earlier non-feedback objects whose fragment data is stored in the buffer. This may allow a determination of whether to remove occluded non-feedback fragment data from the buffer, which may reduce graphics overdraw. In disclosed two-pass techniques, data for feedback objects is first allowed to bypass the buffer for visibility shading, but is then stored in the buffer for a second pass to perform fragment shading to actually determine pixel attributes, which may further reduce overdraw.