公开(公告)号：US20230385201A1

公开(公告)日：2023-11-30

申请号：US18362686

申请日：2023-07-31

Applicant: Apple Inc.

Inventor： Benjiman L. Goodman ,  Terence M. Potter ,  Anjana Rajendran ,  Mark I. Luffel ,  William V. Miller

IPC: G06F12/1009 ,  G06F9/38 ,  G06T1/60 ,  G06T1/20

CPC classification number: G06F12/1009 ,  G06F9/3887 ,  G06T1/60 ,  G06T1/20 ,  G06F2212/657

Abstract: Techniques are disclosed relating to private memory management using a mapping thread, which may be persistent. In some embodiments, a graphics processor is configured to generate a pool of private memory pages for a set of graphics work that includes multiple threads. The processor may maintain a translation table configured to map private memory addresses to virtual addresses based on identifiers of the threads. The processor may execute a mapping thread to receive a request to allocate a private memory page for a requesting thread, select a private memory page from the pool in response to the request, and map the selected page in the translation table for the requesting. The processor may then execute one or more instructions of the requesting thread to access a private memory space, wherein the execution includes translation of a private memory address to a virtual address based on the mapped page in the translation table. The mapping thread may be a persistent thread for which resources are allocated for an entirety of a time interval over which the set of graphics work is executed.

公开(公告)号：US20250068564A1

公开(公告)日：2025-02-27

申请号：US18583520

申请日：2024-02-21

Applicant: Apple Inc.

Inventor： Dimitri Tan ,  William V. Miller

IPC: G06F12/084 ,  G06F12/0811 ,  G06T1/60

Abstract: In disclosed embodiment, a graphics processor is configured to operate on data in multiple memory spaces. Data cache circuitry may cache data for the graphics processor circuitry, including data from multiple memory spaces. The data cache circuitry may include tag circuitry configured to compare the following information from access requests to the data cache circuitry with tags of entries in the data cache circuitry: memory space information and a tag portion of a requested address. The tag portion of a requested address may be different (e.g., a different set of bit indices within the address) for at least two of the multiple memory spaces. Disclosed techniques may advantageously facilitate caching for disparate clients with different cache line sizes, address spaces, etc., e.g., in unified memory architectures.

公开(公告)号：US20150049106A1

公开(公告)日：2015-02-19

申请号：US13970578

申请日：2013-08-19

Applicant: Apple Inc.

Inventor： Andrew M. Havlir ,  Sreevathsa Ramachandra ,  William V. Miller

IPC: G06T1/60

CPC classification number: G06T1/20 ,  G06F9/30098 ,  G06F9/30105 ,  G06F9/3012 ,  G06F9/30123 ,  G06F9/3824 ,  G06F9/3885

Abstract: Techniques are disclosed relating to arbitration of requests to access a register file. In one embodiment, an apparatus includes a write queue and a register file that includes multiple entries. In one embodiment, the apparatus is configured to select a request from a plurality of requests based on a plurality of request characteristics, and write data from the accepted request into a write queue. In one embodiment, the request characteristics include: whether a request is a last request from an agent for a given register file entry and whether the request finishes a previous request. In one embodiment, a final arbiter is configured to select among requests from the write queue, a read queue, and multiple execution pipelines to access banks of the register file in a given cycle.

Abstract translation: 公开了关于访问寄存器文件的请求的仲裁的技术。 在一个实施例中，装置包括写入队列和包括多个条目的寄存器文件。 在一个实施例中，设备被配置为基于多个请求特性从多个请求中选择请求，并将数据从接受的请求写入写入队列。 在一个实施例中，请求特征包括：请求是否是针对给定寄存器文件条目的代理的最后请求以及请求是否完成先前的请求。 在一个实施例中，最终仲裁器被配置为在给定周期中从写入队列，读取队列和多个执行管线的请求中选择访问寄存器文件的存储体。

公开(公告)号：US11714759B2

公开(公告)日：2023-08-01

申请号：US16995450

申请日：2020-08-17

Applicant: Apple Inc.

Inventor： Benjiman L. Goodman ,  Terence M. Potter ,  Anjana Rajendran ,  Mark I. Luffel ,  William V. Miller

IPC: G06F12/00 ,  G06F12/1009 ,  G06F9/38 ,  G06T1/60 ,  G06T1/20

CPC classification number: G06F12/1009 ,  G06F9/3887 ,  G06T1/20 ,  G06T1/60 ,  G06F2212/657

Abstract: Techniques are disclosed relating to private memory management using a mapping thread, which may be persistent. In some embodiments, a graphics processor is configured to generate a pool of private memory pages for a set of graphics work that includes multiple threads. The processor may maintain a translation table configured to map private memory addresses to virtual addresses based on identifiers of the threads. The processor may execute a mapping thread to receive a request to allocate a private memory page for a requesting thread, select a private memory page from the pool in response to the request, and map the selected page in the translation table for the requesting. The processor may then execute one or more instructions of the requesting thread to access a private memory space, wherein the execution includes translation of a private memory address to a virtual address based on the mapped page in the translation table. The mapping thread may be a persistent thread for which resources are allocated for an entirety of a time interval over which the set of graphics work is executed.

公开(公告)号：US09330432B2

公开(公告)日：2016-05-03

申请号：US13970578

申请日：2013-08-19

Applicant: Apple Inc.

Inventor： Andrew M. Havlir ,  Sreevathsa Ramachandra ,  William V. Miller

IPC: G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G06T1/20

CPC classification number: G06T1/20 ,  G06F9/30098 ,  G06F9/30105 ,  G06F9/3012 ,  G06F9/30123 ,  G06F9/3824 ,  G06F9/3885

Abstract: Techniques are disclosed relating to arbitration of requests to access a register file. In one embodiment, an apparatus includes a write queue and a register file that includes multiple entries. In one embodiment, the apparatus is configured to select a request from a plurality of requests based on a plurality of request characteristics, and write data from the accepted request into a write queue. In one embodiment, the request characteristics include: whether a request is a last request from an agent for a given register file entry and whether the request finishes a previous request. In one embodiment, a final arbiter is configured to select among requests from the write queue, a read queue, and multiple execution pipelines to access banks of the register file in a given cycle.

Abstract translation: 公开了关于访问寄存器文件的请求的仲裁的技术。 在一个实施例中，装置包括写入队列和包括多个条目的寄存器文件。 在一个实施例中，设备被配置为基于多个请求特性从多个请求中选择请求，并将数据从接受的请求写入写入队列。 在一个实施例中，请求特征包括：请求是否是针对给定寄存器文件条目的代理的最后请求以及请求是否完成先前的请求。 在一个实施例中，最终仲裁器被配置为在给定周期中从写入队列，读取队列和多个执行管线的请求中选择访问寄存器文件的存储体。