公开(公告)号：US20250086009A1

公开(公告)日：2025-03-13

申请号：US18367710

申请日：2023-09-13

Applicant: Apple Inc.

Inventor： Ronit BANERJEE ,  Karthic A. PALANIAPPAN ,  Bryan R. HINCH ,  John G. DORSEY

IPC: G06F9/48 ,  G06F9/54

Abstract: Systems, methods, and apparatuses disclosed herein can operate in different performance states that provide different energy performance tradeoffs and, in some embodiments, can dynamically switch between these different performance states. These systems, methods, and apparatuses can estimate specific timeframes that workloads are to be completed. These systems, methods, and apparatuses can identify one or more processes that are being executed to perform the workloads. These systems, methods, and apparatuses can dynamically provision one or more performance states from among these different performance states to execute the process to complete the workloads within the specific timeframes. These systems, methods, and apparatuses can dynamically provision the one or more performance states for the one or more process that optimizes power consumption and/or performance while completing the workloads within the specific timeframes.

公开(公告)号：US20150348223A1

公开(公告)日：2015-12-03

申请号：US14489356

申请日：2014-09-17

Applicant: Apple Inc.

Inventor： John G. DORSEY ,  Keith COX ,  Cyril de la CROPTE de CHANTERAC ,  Karl D. VULKAN

IPC: G06T1/20 ,  G09G5/18 ,  G06T1/60 ,  G06T13/80

CPC classification number: G06T1/20 ,  G06T13/80 ,  G09G5/18 ,  G09G5/363 ,  G09G2330/021 ,  G09G2340/0435 ,  G09G2340/045

Abstract: The embodiments set forth a technique for targeted scaling of the voltage and/or frequency of hardware components included in a mobile computing device. One embodiment involves independently analyzing the individual frame rates of each animation within a user interface (UI) of a mobile computing device instead of analyzing the frame rate of the UI as a whole. This can involve establishing, for each animation being displayed within the UI, a corresponding performance control pipeline that generates a control signal for scaling a performance mode of the hardware components (e.g., a Central Processing Unit (CPU)) included in the mobile computing device. In this manner, the control signals generated by the performance control pipelines can be aggregated to produce a control signal that causes a power management component to scale the performance mode(s) of the hardware components.

Abstract translation: 这些实施例提出了用于针对包括在移动计算设备中的硬件组件的电压和/或频率进行目标缩放的技术。 一个实施例涉及独立地分析移动计算设备的用户界面（UI）内的每个动画的各个帧速率，而不是分析整个UI的帧速率。 这可以涉及为在UI内显示的每个动画建立相应的性能控制流水线，其生成用于缩放包括在移动计算设备中的硬件组件（例如，中央处理单元（CPU））的性能模式的控制信号 。 以这种方式，可以聚合由性能控制管线产生的控制信号，以产生控制信号，该控制信号使得功率管理部件缩放硬件部件的性能模式。

公开(公告)号：US20210157700A1

公开(公告)日：2021-05-27

申请号：US17098262

申请日：2020-11-13

Applicant: Apple Inc.

Inventor： John G. DORSEY ,  Andrei DOROFEEV ,  Keith COX

IPC: G06F11/30 ,  G06F11/34 ,  G06F11/07 ,  G06F9/50 ,  G06F9/30

Abstract: A device implementing adaptive memory performance control by thread group may include a memory and at least one processor. The at least one processor may be configured to execute a group of threads on one or more cores. The at least one processor may be configured to monitor a plurality of metrics corresponding to the group of threads executing on one or more cores. The metrics may include, for example, a core stall ratio and/or a power metric. The at least one processor may be configured to determine, based at least in part on the plurality of metrics, a memory bandwidth constraint with respect to the group of threads executing on the one or more cores. The at least one processor may be configured to, in response to determining the memory bandwidth constraint, increase a memory performance corresponding to the group of threads executing on the one or more cores.

公开(公告)号：US20150348228A1

公开(公告)日：2015-12-03

申请号：US14821665

申请日：2015-08-07

Applicant: Apple Inc.

Inventor： John G. DORSEY ,  James S. ISMAIL ,  Keith COX ,  Gaurav KAPOOR

IPC: G06T1/20 ,  G09G5/18 ,  G09G5/00

CPC classification number: G09G5/003 ,  G06F1/20 ,  G06F1/26 ,  G06F1/324 ,  G06F1/3296 ,  G06T1/20 ,  G06T1/60 ,  G06T13/80 ,  G06T2200/28 ,  G09G5/18 ,  G09G2354/00 ,  G09G2360/08 ,  G09G2360/127 ,  Y02D10/126 ,  Y02D10/172

Abstract: The invention provides a technique for targeted scaling of the voltage and/or frequency of a processor included in a computing device. One embodiment involves scaling the voltage/frequency of the processor based on the number of frames per second being input to a frame buffer in order to reduce or eliminate choppiness in animations shown on a display of the computing device. Another embodiment of the invention involves scaling the voltage/frequency of the processor based on a utilization rate of the GPU in order to reduce or eliminate any bottleneck caused by slow issuance of instructions from the CPU to the GPU. Yet another embodiment of the invention involves scaling the voltage/frequency of the CPU based on specific types of instructions being executed by the CPU. Further embodiments include scaling the voltage and/or frequency of a CPU when the CPU executes workloads that have characteristics of traditional desktop/laptop computer applications.

Abstract translation: 本发明提供了一种用于针对包括在计算设备中的处理器的电压和/或频率进行目标缩放的技术。 一个实施例涉及基于每秒输入帧缓冲器的帧数来缩放处理器的电压/频率，以便减少或消除在计算设备的显示器上显示的动画中的笨拙。 本发明的另一实施例涉及基于GPU的利用率来缩放处理器的电压/频率，以便减少或消除由CPU向GPU缓慢发出指令所引起的任何瓶颈。 本发明的另一个实施例涉及根据由CPU执行的特定类型的指令来调整CPU的电压/频率。 另外的实施例包括在CPU执行具有传统台式/膝上型计算机应用的特征的工作负载时缩放CPU的电压和/或频率。

公开(公告)号：US20230040310A1

公开(公告)日：2023-02-09

申请号：US17392929

申请日：2021-08-03

Applicant: Apple Inc.

Inventor： John G. DORSEY ,  Bryan R. HINCH ,  Ronit BANERJEE ,  Kushal DALMIA ,  Daniel A. CHIMENE ,  Jaidev P. PATWARDHAN

IPC: G06F9/50

Abstract: Embodiments include an asymmetric multiprocessing (AMP) system having a first central processing unit (CPU) cluster comprising a first core type, and a second CPU cluster comprising a second core type, where the AMP system can update a thread metric for a first thread running on the first CPU cluster based at least on: a past shared resource overloaded metric of the first CPU cluster, and on-core metrics of the first thread. The on-core metrics of the first thread can indicate that first thread contributes to contention of the same shared resource corresponding to the past shared resource overloaded metric of the first CPU cluster. The AMP system can assign the first thread to a different CPU cluster while other threads of the same thread group remain assigned to the first CPU cluster. The thread metric can include a Matrix Extension (MX) thread flag or a Bus Interface Unit (BIU) thread flag.

公开(公告)号：US20140164757A1

公开(公告)日：2014-06-12

申请号：US13913307

申请日：2013-06-07

Applicant: Apple Inc.

Inventor： John G. DORSEY ,  James S. ISMAIL ,  Keith COX ,  Gaurav KAPOOR

IPC: G06F1/32

CPC classification number: G09G5/003 ,  G06F1/20 ,  G06F1/26 ,  G06F1/324 ,  G06F1/3296 ,  G06T1/20 ,  G06T1/60 ,  G06T13/80 ,  G06T2200/28 ,  G09G5/18 ,  G09G2354/00 ,  G09G2360/08 ,  G09G2360/127 ,  Y02D10/126 ,  Y02D10/172

Abstract: The invention provides a technique for targeted scaling of the voltage and/or frequency of a processor included in a computing device. One embodiment involves scaling the voltage/frequency of the processor based on the number of frames per second being input to a frame buffer in order to reduce or eliminate choppiness in animations shown on a display of the computing device. Another embodiment of the invention involves scaling the voltage/frequency of the processor based on a utilization rate of the GPU in order to reduce or eliminate any bottleneck caused by slow issuance of instructions from the CPU to the GPU. Yet another embodiment of the invention involves scaling the voltage/frequency of the CPU based on specific types of instructions being executed by the CPU. Further embodiments include scaling the voltage and/or frequency of a CPU when the CPU executes workloads that have characteristics of traditional desktop/laptop computer applications.

Abstract translation: 本发明提供了一种用于针对包括在计算设备中的处理器的电压和/或频率进行目标缩放的技术。 一个实施例涉及基于每秒输入帧缓冲器的帧数来缩放处理器的电压/频率，以便减少或消除在计算设备的显示器上显示的动画中的笨拙。 本发明的另一实施例涉及基于GPU的利用率来缩放处理器的电压/频率，以便减少或消除由CPU向GPU缓慢发出指令所引起的任何瓶颈。 本发明的另一个实施例涉及根据由CPU执行的特定类型的指令来调整CPU的电压/频率。 另外的实施例包括在CPU执行具有传统台式/膝上型计算机应用的特征的工作负载时缩放CPU的电压和/或频率。

公开(公告)号：US20250093932A1

公开(公告)日：2025-03-20

申请号：US18468467

申请日：2023-09-15

Applicant: Apple Inc.

Inventor： John G. DORSEY ,  Bryan R. Hinch ,  Ronit Banerjee ,  Karthic A. Palaniappan

IPC: G06F1/28

Abstract: Some embodiments include a system, apparatus, method, and computer program product for memory hierarchy power management. Some embodiments include a performance controller that balances memory hierarchy power and compute power to maintain package-level power efficiency of a systems-on-a-chip (SoC)-memory package. The performance controller can determine a ratio of memory hierarchy power to compute agent power, compare the ratio against a threshold value, and based on the comparison, determine how to manage memory hierarchy power. When the energy costs of the memory hierarchy power are large relative to the energy costs of the compute agent power, some embodiments include changing a performance state of a fabric and/or memory to increase the power efficiency of the overall SoC-memory package, even though a number of memory stall cycles experienced by the compute agent may increase.

公开(公告)号：US20230067109A1

公开(公告)日：2023-03-02

申请号：US17893913

申请日：2022-08-23

Applicant: Apple Inc.

Inventor： Bryan R. HINCH ,  John G. DORSEY ,  Ronit BANERJEE ,  Kushal DALMIA ,  Daniel A. CHIMENE ,  Jaidev P. PATWARDHAN

IPC: G06F15/78 ,  G06F11/34 ,  G06F9/48

Abstract: Embodiments include an asymmetric multiprocessing (AMP) system having two or more central processing unit (CPU) clusters of a first core type and a CPU cluster of a second core type. Some embodiments include determining a control effort for an active thread group, and assigning the thread group to a first performance island according to the control effort range of the first performance island. The first performance island can include a first CPU cluster of the first core type, where a second performance island includes a second CPU cluster of the first core type, where the second performance island corresponds to a different control effort range than the first performance island. Some embodiments include assigning the first CPU cluster as a preferred CPU cluster of the first thread group, and transmitting a first signal identifying the first CPU cluster as the preferred CPU cluster assigned to the first thread group.

公开(公告)号：US20160357243A1

公开(公告)日：2016-12-08

申请号：US14869854

申请日：2015-09-29

Applicant: Apple Inc.

Inventor： John G. DORSEY ,  Keith COX

IPC: G06F1/32

CPC classification number: G06F1/3228 ,  G06F1/3206 ,  G06F1/324 ,  G06F1/329 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172 ,  Y02D10/24

Abstract: The embodiments set forth a technique for providing reactive performance throttle engagement information to controller limiters, which are implemented as closed loop structures that analyze the information against target reactive performance throttle engagement rates and produce control effort limits. When reactive performance throttle engagement rates are below the target, controllers issue control efforts in a normal fashion such that they are not influenced by the control effort limits produced by the controller limiters. However, the controller limiters are also configured such that when reactive performance throttle engagement rates are above the target, the controllers issue control efforts in a modified fashion—specifically, in accordance with the control effort limits produced by the controller limiters. In this manner, control effort limits can effectively clamp the control efforts when particular conditions—such as excessive reactive performance throttle engagement rates—are being met.

Abstract translation: 实施例提出了一种用于向控制器限制器提供无功性能节流阀接合信息的技术，控制器限制器被实现为闭环结构，其分析针对目标反应性能油门接合速率的信息并产生控制力限制。 当无功性能油门参与率低于目标时，控制器以正常方式发出控制措施，使其不受控制器限制器产生的控制力限制的影响。 然而，控制器限制器还被配置成使得当无功性能油门接合速率高于目标时，控制器以修改的方式发出控制工作，具体地，根据由控制器限制器产生的控制力限制。 以这种方式，当满足特定条件（例如过大的反应性节流阀接合速率）时，控制力限制可以有效地钳制控制工作。