公开(公告)号：US20240077932A1

公开(公告)日：2024-03-07

申请号：US18122410

申请日：2023-03-16

Applicant: Apple Inc.

Inventor： Talbott M. Houk ,  Wenxun Huang ,  Nikola Jovanovic ,  Floyd L. Dankert ,  Sanjay Pant ,  Alessandro Molari ,  Siarhei Meliukh ,  Nicola Florio ,  Ludmil N. Nikolov ,  Nathan F. Hanagami ,  Hartmut Sturm ,  Di Zhao ,  Chad L. Olson ,  John J. Sullivan ,  Seyedeh Maryam Mortazavi Zanjani ,  Tristan R. Hudson ,  Jay B. Fletcher ,  Jonathan A. Dutra

IPC: G06F1/3296 ,  G06F1/3212 ,  G06F1/3234

CPC classification number: G06F1/3296 ,  G06F1/3212 ,  G06F1/3278

Abstract: The present disclosure describes a system with a power management device, a wakeup circuit, a battery management device, and a connector. During a powered down mode of operation, the battery management device can provide, via the connector, a bias voltage to the wakeup circuit. In response to a wakeup switch being activated, the battery management device can provide a power supply (e.g., from a battery) to the power management device. Benefits of the wakeup circuit include (1) a reduction of battery consumption—and thus improving battery lifetime—when the electronic system is in a powered down mode of operation because the wakeup circuit has lower number of active components compared to other designs and (2) a non-complex wakeup circuit design because one or more existing connector interconnects between the power management device and the battery management device can be re-used during electronic system's powered down mode of operation.

公开(公告)号：US20240038310A1

公开(公告)日：2024-02-01

申请号：US17874100

申请日：2022-07-26

Applicant: Apple Inc.

Inventor： John J. Sullivan ,  James M. Hollabaugh ,  Jason W. Brinsfield ,  Calvin M. Ryan ,  Andreas Adler

IPC: G11C16/30 ,  G11C16/10 ,  G11C16/14 ,  G11C16/32

CPC classification number: G11C16/30 ,  G11C16/102 ,  G11C16/14 ,  G11C16/32

Abstract: Techniques for protecting non-volatile memory (NVM) from power cycle interruptions during memory operations are disclosed. A power management integrated circuit (PMIC) coupled to a memory circuit with NVM implements the various techniques disclosed. When a power reset signal is asserted to a PMIC, the PMIC may delay initiation of the power reset cycle when it detects that the NVM coupled to the PMIC is active to prevent corruption of the NVM by the power reset cycle. The PMIC may detect the activity level of the NVM based on an activity output signal that indicates whether the NVM is active (e.g., programming or erasing) or inactive.