公开(公告)号：US10007616B1

公开(公告)日：2018-06-26

申请号：US15062448

申请日：2016-03-07

Applicant: Apple Inc.

Inventor： Brett S. Feero ,  David J. Williamson ,  Jonathan J. Tyler ,  Mary D. Brown

IPC: G06F12/08 ,  G06F12/0891 ,  G06F12/0862 ,  G06F12/0875 ,  G06F12/0831 ,  G06F12/128

CPC classification number: G06F12/0875 ,  G06F9/3802 ,  G06F9/3806 ,  G06F12/0862 ,  G06F12/12 ,  G06F2212/1016 ,  G06F2212/452 ,  G06F2212/502

Abstract: In an embodiment, an apparatus includes a cache memory and a control circuit. The control circuit may be configured to pre-fetch and store a first quantity of instruction data in response to a determination that a first pre-fetch operation request is received after a reset and prior to a first end condition. The first end condition may depend on an amount of unused storage in the cache memory. The control circuit may be further configured to pre-fetch and store a second quantity of instruction data in response to a determination that a second pre-fetch operation request is received after the first end condition. The second quantity may be less than the first quantity.