公开(公告)号：US11487667B1

公开(公告)日：2022-11-01

申请号：US17397429

申请日：2021-08-09

Applicant: Apple Inc.

Inventor： Ronald P. Hall ,  Mary D. Brown ,  Balaji Kadambi ,  Mahesh K. Reddy

IPC: G06F12/0862

Abstract: A cache subsystem is disclosed. The cache subsystem includes a cache configured to store information in cache lines arranged in a plurality of ways. A requestor circuit generates a request to access a particular cache line in the cache. A prediction circuit is configured to generate a prediction of which of the ways includes the particular cache line. A comparison circuit verifies the prediction by comparing a particular address tag associated with the particular cache line to a cache tag corresponding to a predicted one of the ways. Responsive to determining that the prediction was correct, a confirmation indication is stored indicating the correct prediction. For a subsequent request for the particular cache line, the cache is configured to forego a verification of the prediction that the particular cache line is included in the one of the ways based on the confirmation indication.

公开(公告)号：US20240176744A1

公开(公告)日：2024-05-30

申请号：US18438111

申请日：2024-02-09

Applicant: Apple Inc.

Inventor： Ronald P. Hall ,  Mary D. Brown ,  Balaji Kadambi ,  Mahesh K. Reddy

IPC: G06F12/0862

CPC classification number: G06F12/0862 ,  G06F2212/6032

Abstract: A cache subsystem is disclosed. The cache subsystem includes a cache configured to store information in cache lines arranged in a plurality of ways. A requestor circuit generates a request to access a particular cache line in the cache. A prediction circuit is configured to generate a prediction of which of the ways includes the particular cache line. A comparison circuit verifies the prediction by comparing a particular address tag associated with the particular cache line to a cache tag corresponding to a predicted one of the ways. Responsive to determining that the prediction was correct, a confirmation indication is stored indicating the correct prediction. For a subsequent request for the particular cache line, the cache is configured to forego a verification of the prediction that the particular cache line is included in the one of the ways based on the confirmation indication.

公开(公告)号：US11880308B2

公开(公告)日：2024-01-23

申请号：US17933603

申请日：2022-09-20

Applicant: Apple Inc.

Inventor： Ronald P. Hall ,  Mary D. Brown ,  Balaji Kadambi ,  Mahesh K. Reddy

IPC: G06F12/0862

CPC classification number: G06F12/0862 ,  G06F2212/6032

Abstract: A cache subsystem is disclosed. The cache subsystem includes a cache configured to store information in cache lines arranged in a plurality of ways. A requestor circuit generates a request to access a particular cache line in the cache. A prediction circuit is configured to generate a prediction of which of the ways includes the particular cache line. A comparison circuit verifies the prediction by comparing a particular address tag associated with the particular cache line to a cache tag corresponding to a predicted one of the ways. Responsive to determining that the prediction was correct, a confirmation indication is stored indicating the correct prediction. For a subsequent request for the particular cache line, the cache is configured to forego a verification of the prediction that the particular cache line is included in the one of the ways based on the confirmation indication.

公开(公告)号：US10007616B1

公开(公告)日：2018-06-26

申请号：US15062448

申请日：2016-03-07

Applicant: Apple Inc.

Inventor： Brett S. Feero ,  David J. Williamson ,  Jonathan J. Tyler ,  Mary D. Brown

IPC: G06F12/08 ,  G06F12/0891 ,  G06F12/0862 ,  G06F12/0875 ,  G06F12/0831 ,  G06F12/128

CPC classification number: G06F12/0875 ,  G06F9/3802 ,  G06F9/3806 ,  G06F12/0862 ,  G06F12/12 ,  G06F2212/1016 ,  G06F2212/452 ,  G06F2212/502

Abstract: In an embodiment, an apparatus includes a cache memory and a control circuit. The control circuit may be configured to pre-fetch and store a first quantity of instruction data in response to a determination that a first pre-fetch operation request is received after a reset and prior to a first end condition. The first end condition may depend on an amount of unused storage in the cache memory. The control circuit may be further configured to pre-fetch and store a second quantity of instruction data in response to a determination that a second pre-fetch operation request is received after the first end condition. The second quantity may be less than the first quantity.

公开(公告)号：US20230084736A1

公开(公告)日：2023-03-16

申请号：US17933603

申请日：2022-09-20

Applicant: Apple Inc.

Inventor： Ronald P. Hall ,  Mary D. Brown ,  Balaji Kadambi ,  Mahesh K. Reddy

IPC: G06F12/0862

Abstract: A cache subsystem is disclosed. The cache subsystem includes a cache configured to store information in cache lines arranged in a plurality of ways. A requestor circuit generates a request to access a particular cache line in the cache. A prediction circuit is configured to generate a prediction of which of the ways includes the particular cache line. A comparison circuit verifies the prediction by comparing a particular address tag associated with the particular cache line to a cache tag corresponding to a predicted one of the ways. Responsive to determining that the prediction was correct, a confirmation indication is stored indicating the correct prediction. For a subsequent request for the particular cache line, the cache is configured to forego a verification of the prediction that the particular cache line is included in the one of the ways based on the confirmation indication.

公开(公告)号：US20240028339A1

公开(公告)日：2024-01-25

申请号：US17814729

申请日：2022-07-25

Applicant: Apple Inc.

Inventor： Niket K. Choudhary ,  Mary D. Brown ,  Ethan R. Schuchman ,  Ronald P. Hall ,  Ian D. Kountanis ,  Douglas C. Holman ,  Ilhyun Kim ,  Abhishek Kumar ,  Siavash Zangeneh Kamali

IPC: G06F9/38 ,  G06F12/0875

CPC classification number: G06F9/3802 ,  G06F12/0875 ,  G06F2212/452

Abstract: An apparatus includes an instruction cache circuit and an instruction fetch circuit. The instruction fetch circuit is configured to retrieve, from the instruction cache circuit, a fetch group that includes a plurality of instructions for execution by a processing circuit, and to make a determination that the fetch group includes a control transfer instruction that is predicted to be taken. A target address associated with the control transfer instruction is directed to an instruction within the fetch group. The instruction fetch circuit is further configured to, based on the determination, alter instructions within the fetch group in a manner that is based on a type of the control transfer instruction.