公开(公告)号：US20230298302A1

公开(公告)日：2023-09-21

申请号：US17695038

申请日：2022-03-15

Applicant: Apple Inc.

Inventor： Assaf Metuki ,  Danny Gal ,  Liran Fishel

IPC: G06V10/46 ,  G06V10/74 ,  G06V10/75

CPC classification number: G06V10/46 ,  G06V10/751 ,  G06V10/761

Abstract: Embodiments of the present disclosure relate to sequentially loading keypoint descriptors of a previous image and comparing them with a plurality of keypoint descriptors of a current image. The keypoint descriptors of the previous image are stored and accessed from a system memory while the keypoint descriptors of the current image are stored and accessed from a local memory. Hence, the keypoint descriptors of the previous image are received only once at a descriptor match circuit while the keypoint descriptors of the current image are received multiple times for comparison against different keypoint descriptors of the previous image.

公开(公告)号：US11614937B1

公开(公告)日：2023-03-28

申请号：US17566193

申请日：2021-12-30

Applicant: Apple Inc.

Inventor： Liran Fishel ,  Danny Gal ,  Nir Nissan ,  Etai Zaltsman

IPC: G06F9/30

Abstract: Embodiments of the present disclosure relate to an accelerator circuit with a dynamic immediate values table (IVT). The accelerator circuit includes an instruction memory, a data memory, and a vector circuit with the IVT storing multiple immediate values at multiple entries. The vector circuit reads a subset of instructions from the instruction memory, each instruction including at least one corresponding pointer to at least one corresponding entry in the IVT. The vector circuit further receives a subset of input data from the data memory corresponding to the subset of instructions. The vector circuit performs a respective operation in accordance with each instruction from the subset of instructions using a corresponding data vector of the received subset of input data identified in each instruction and at least one corresponding immediate value from the IVT pointed by the at least one corresponding pointer to generate corresponding output data.

公开(公告)号：US11507702B2

公开(公告)日：2022-11-22

申请号：US16674909

申请日：2019-11-05

Applicant: Apple Inc.

Inventor： Liran Fishel ,  Zhimin Chen

IPC: G06F21/74 ,  G06F9/54 ,  G06F21/57 ,  G06N3/063

Abstract: Embodiments relate to switching a neural processor circuit between non-secure and secure modes. A security controller of the neural processor circuit indicates that a transition from the non-secure mode to the secure mode is to occur. The security controller waits for a neural task manager of the neural processor circuit to clear out any existing non-secure tasks in queues. After the existing non-secure mode tasks are cleared, the security controller switches the neural processor circuit to the secure mode. While in the secure mode, secure tasks are added to one or more queues and executed, and data for processing in the neural processor circuit is received from a secure source. The neural processor circuit may to transition back to the non-secure mode when all secure mode tasks are completed.

公开(公告)号：US20210133361A1

公开(公告)日：2021-05-06

申请号：US16674909

申请日：2019-11-05

Applicant: Apple Inc.

Inventor： Liran Fishel ,  Zhimin Chen

IPC: G06F21/74 ,  G06F21/57 ,  G06N3/063 ,  G06F9/54

Abstract: Embodiments relate to switching a neural processor circuit between non-secure and secure modes. A security controller of the neural processor circuit indicates that a transition from the non-secure mode to the secure mode is to occur. The security controller waits for a neural task manager of the neural processor circuit to clear out any existing non-secure tasks in queues. After the existing non-secure mode tasks are cleared, the security controller switches the neural processor circuit to the secure mode. While in the secure mode, secure tasks are added to one or more queues and executed, and data for processing in the neural processor circuit is received from a secure source. The neural processor circuit may to transition back to the non-secure mode when all secure mode tasks are completed.

公开(公告)号：US11989640B2

公开(公告)日：2024-05-21

申请号：US17991373

申请日：2022-11-21

Applicant: Apple Inc.

Inventor： Erik Norden ,  Liran Fishel ,  Sung Hee Park ,  Jaewon Shin ,  Christopher L. Mills ,  Seungjin Lee ,  Fernando A. Mujica

IPC: G06N3/04 ,  G06F1/3296 ,  G06N3/08

CPC classification number: G06N3/04 ,  G06F1/3296 ,  G06N3/08

Abstract: Embodiments relate to a neural processor circuit with scalable architecture for instantiating one or more neural networks. The neural processor circuit includes a data buffer coupled to a memory external to the neural processor circuit, and a plurality of neural engine circuits. To execute tasks that instantiate the neural networks, each neural engine circuit generates output data using input data and kernel coefficients. A neural processor circuit may include multiple neural engine circuits that are selectively activated or deactivated according to configuration data of the tasks. Furthermore, an electronic device may include multiple neural processor circuits that are selectively activated or deactivated to execute the tasks.

公开(公告)号：US11740932B2

公开(公告)日：2023-08-29

申请号：US15971276

申请日：2018-05-04

Applicant: Apple Inc.

Inventor： Liran Fishel ,  Erik K. Norden

IPC: G06F3/00 ,  G06F9/48 ,  G06N3/063 ,  G06F9/54 ,  G06F13/28 ,  G06F13/16 ,  G06N3/045

CPC classification number: G06F9/4843 ,  G06F9/544 ,  G06F13/1673 ,  G06F13/28 ,  G06N3/045 ,  G06N3/063

Abstract: Embodiments relate to managing tasks that when executed by a neural processor circuit instantiates a neural network. A neural task manager circuit within the neural processor circuit can switch between tasks in different task queues. Each task queue is configured to store a reference to a task list of tasks for instantiating a neural network. Each task queue can also be assigned a priority parameter. While the neural processor circuit is executing tasks of a first task list and prior to completion of each task, the neural task manager circuit can switch between task queues according to the priority parameters for execution of tasks of a second task list by the neural processor circuit. The neural processor circuit includes one or more neural engine circuits that are configured to perform neural operations by executing the tasks assigned by the task manager.

公开(公告)号：US20230267168A1

公开(公告)日：2023-08-24

申请号：US17675369

申请日：2022-02-18

Applicant: Apple Inc.

Inventor： Liran Fishel ,  Danny Gal ,  Nir Nissan ,  Etai Zaltsman

IPC: G06F17/16

CPC classification number: G06F17/16

Abstract: Embodiments of the present disclosure relate to a vector circuit in an accelerator circuit for performing vector and scalar operations. The vector circuit reads a subset of instructions from an instruction memory, each instruction including an identification of at least a portion of a first vector and an identification of at least a portion of a second vector. The vector circuit further receives a portion of input data from a data memory corresponding to the subset of instructions. The vector circuit performs a respective operation in accordance with each instruction on at least one first element of the first vector and at least one second element of the second vector to generate at least one output element of an output vector. Each instruction indicates positions in respective vectors for the at least one first element, the at least one second element and the at least one output element.

公开(公告)号：US20230016350A1

公开(公告)日：2023-01-19

申请号：US17948231

申请日：2022-09-20

Applicant: Apple Inc.

Inventor： Liran Fishel ,  Asaaf Metuki ,  Chuhan Min ,  Wai Yu Trevor Tsang

IPC: G06K9/62 ,  G06V10/40 ,  G06V10/24 ,  G06V10/75

Abstract: Embodiments relate to generating keypoint descriptors of the keypoints. An apparatus includes a pyramid image generator circuit and a keypoint descriptor generator circuit. The pyramid image generator circuit generates an image pyramid from an input image. The keypoint descriptor generator circuit determines intensity values of sample points in the pyramid images for a keypoint and determines comparison results of comparisons between the intensity values of pairs of the sample points. The keypoint descriptor generator circuit generate bit values defining the comparison results for the keypoint, each bit value corresponding with one of the comparison results, and generate a sequence of the bit values defining an ordering of the comparison results based on importance levels of the comparisons, where the importance level of each comparison defines how much the comparison is representative of features. Bit values for comparisons having the lowest importance levels may be excluded from the sequence.

公开(公告)号：US11537838B2

公开(公告)日：2022-12-27

申请号：US15971882

申请日：2018-05-04

Applicant: Apple Inc.

Inventor： Erik K. Norden ,  Liran Fishel ,  Sung Hee Park ,  Jaewon Shin ,  Christopher L. Mills ,  Seungjin Lee ,  Fernando A. Mujica

IPC: G06N3/04 ,  G06F1/3296 ,  G06N3/08

Abstract: Embodiments relate to a neural processor circuit with scalable architecture for instantiating one or more neural networks. The neural processor circuit includes a data buffer coupled to a memory external to the neural processor circuit, and a plurality of neural engine circuits. To execute tasks that instantiate the neural networks, each neural engine circuit generates output data using input data and kernel coefficients. A neural processor circuit may include multiple neural engine circuits that are selectively activated or deactivated according to configuration data of the tasks. Furthermore, an electronic device may include multiple neural processor circuits that are selectively activated or deactivated to execute the tasks.

公开(公告)号：US20220286604A1

公开(公告)日：2022-09-08

申请号：US17195520

申请日：2021-03-08

Applicant: Apple Inc.

Inventor： David R. Pope ,  Liran Fishel ,  Assaf Metuki ,  Muge Wang

IPC: H04N5/232 ,  G06K9/46 ,  H04N5/76

Abstract: Embodiments relate to extracting features from images, such as by identifying keypoints and generating keypoint descriptors of the keypoints. An apparatus includes a pyramid image generator circuit, a keypoint descriptor generator circuit, and a pyramid image buffer. The pyramid image generator circuit generates an image pyramid from an input image. The keypoint descriptor generator circuit processes the pyramid images for keypoint descriptor generation. The pyramid image buffer stores different portions of the pyramid images generated by the pyramid image generator circuit at different times and provides the stored portions of the pyramid images to the keypoint descriptor generator circuit for keypoint descriptor generation. When first portions of the pyramid images are no longer needed for the keypoint descriptor generation, the first portions are removed from the pyramid image buffer to provide space for second portions of the pyramid images that are needed for the keypoint descriptor generation.