公开(公告)号：US11210100B2

公开(公告)日：2021-12-28

申请号：US16242151

申请日：2019-01-08

Applicant: Apple Inc.

Inventor： Aditya Kesiraju ,  Brett S. Feero ,  Nikhil Gupta ,  Viney Gautam

IPC: G06F9/38 ,  G06F9/30 ,  G06F9/48 ,  G06F9/52

Abstract: In an embodiment, a processor includes a buffer in an interface unit. The buffer may be used to accumulate coprocessor instructions to be transmitted to a coprocessor. In an embodiment, the processor issues the coprocessor instructions to the buffer when ready to be issued to the coprocessor. The interface unit may accumulate the coprocessor instructions in the buffer, generating a bundle of instructions. The bundle may be closed based on various predetermined conditions and then the bundle may be transmitted to the coprocessor. If a sequence of coprocessor instructions appears consecutively in a program, the rate at which the instructions are provided to the coprocessor (on average) at least matches the rate at which the coprocessor consumes the instructions, in an embodiment.

公开(公告)号：US11176045B2

公开(公告)日：2021-11-16

申请号：US16832893

申请日：2020-03-27

Applicant: Apple Inc.

Inventor： Stephan G. Meier ,  Tyler J. Huberty ,  Nikhil Gupta

IPC: G06F12/00 ,  G06F12/0862 ,  G06F9/38

Abstract: In an embodiment, a processor includes a plurality of prefetch circuits configured to prefetch data into a data cache. A primary prefetch circuit may be configured to generate first prefetch requests in response to a demand access, and may be configured to invoke a second prefetch circuit in response to the demand access. The second prefetch circuit may implement a different prefetch mechanism than the first prefetch circuit. If the second prefetch circuit reaches a threshold confidence level in prefetching for the demand access, the second prefetch circuit may communicate an indication to the primary prefetch circuit. The primary prefetch circuit may reduce a number of prefetch requests generated for the demand access responsive to the communication from the second prefetch circuit.

公开(公告)号：US20220137975A1

公开(公告)日：2022-05-05

申请号：US17527872

申请日：2021-11-16

Applicant: Apple Inc.

Inventor： Aditya Kesiraju ,  Brett S. Feero ,  Nikhil Gupta ,  Viney Gautam

IPC: G06F9/38 ,  G06F9/30 ,  G06F9/48 ,  G06F9/52

Abstract: In an embodiment, a processor includes a buffer in an interface unit. The buffer may be used to accumulate coprocessor instructions to be transmitted to a coprocessor. In an embodiment, the processor issues the coprocessor instructions to the buffer when ready to be issued to the coprocessor. The interface unit may accumulate the coprocessor instructions in the buffer, generating a bundle of instructions. The bundle may be closed based on various predetermined conditions and then the bundle may be transmitted to the coprocessor. If a sequence of coprocessor instructions appears consecutively in a program, the rate at which the instructions are provided to the coprocessor (on average) at least matches the rate at which the coprocessor consumes the instructions, in an embodiment.

公开(公告)号：US11175917B1

公开(公告)日：2021-11-16

申请号：US17018875

申请日：2020-09-11

Applicant: Apple Inc.

Inventor： Mridul Agarwal ,  Kulin N. Kothari ,  Nikhil Gupta

IPC: G06F9/38 ,  G06F11/14 ,  G06F9/30 ,  G06F9/48

Abstract: In an embodiment, a processor comprises a reservation station that issues a first load operation for execution, a store queue, and a replayed load buffer coupled in parallel with the reservation station. During execution of the first load operation, the store queue detects that the first load operation hits on a first store operation in the store queue that lacks store data and causes a replay of the first load operation. The replayed load buffer captures an identifier of the first load operation and the first store operation based on the replay of the first load operation, wherein the replayed load buffer monitors the reservation station for issuance of a first store data operation corresponding to the first store operation and issues the first load operation for reexecution based on the issuance of the first store data operation.

公开(公告)号：US10776125B2

公开(公告)日：2020-09-15

申请号：US16210231

申请日：2018-12-05

Applicant: Apple Inc.

Inventor： Aditya Kesiraju ,  Brett S. Feero ,  Nikhil Gupta

IPC: G06F9/38 ,  G06F12/0815 ,  G06F12/084

Abstract: In an embodiment, at least one CPU processor and at least one coprocessor are included in a system. The CPU processor may issue operations to the coprocessor to perform, including load/store operations. The CPU processor may generate the addresses that are accessed by the coprocessor load/store operations, as well as executing its own CPU load/store operations. The CPU processor may include a memory ordering table configured to track at least one memory region within which there are outstanding coprocessor load/store memory operations that have not yet completed. The CPU processor may delay CPU load/store operations until the outstanding coprocessor load/store operations are complete. In this fashion, the proper ordering of CPU load/store operations and coprocessor load/store operations may be maintained.

公开(公告)号：US20200218540A1

公开(公告)日：2020-07-09

申请号：US16242151

申请日：2019-01-08

Applicant: Apple Inc.

Inventor： Aditya Kesiraju ,  Brett S. Feero ,  Nikhil Gupta ,  Viney Gautam

IPC: G06F9/38 ,  G06F9/30 ,  G06F9/48 ,  G06F9/52

Abstract: In an embodiment, a processor includes a buffer in an interface unit. The buffer may be used to accumulate coprocessor instructions to be transmitted to a coprocessor. In an embodiment, the processor issues the coprocessor instructions to the buffer when ready to be issued to the coprocessor. The interface unit may accumulate the coprocessor instructions in the buffer, generating a bundle of instructions. The bundle may be closed based on various predetermined conditions and then the bundle may be transmitted to the coprocessor. If a sequence of coprocessor instructions appears consecutively in a program, the rate at which the instructions are provided to the coprocessor (on average) at least matches the rate at which the coprocessor consumes the instructions, in an embodiment.

公开(公告)号：US10331567B1

公开(公告)日：2019-06-25

申请号：US15435910

申请日：2017-02-17

Applicant: Apple Inc.

Inventor： Stephan G. Meier ,  Tyler J. Huberty ,  Nikhil Gupta ,  Francesco Spadini ,  Gideon Levinsky

IPC: G06F12/08 ,  G06F12/0862 ,  G06F12/12

Abstract: A prefetch circuit may include a memory, each entry of which may store an address and other prefetch data used to generate prefetch requests. For each entry, there may be at least one “quality factor” (QF) that may control prefetch request generation for that entry. A global quality factor (GQF) may control generation of prefetch requests across the plurality of entries. The prefetch circuit may include one or more additional prefetch mechanisms. For example, a stride-based prefetch circuit may be included that may generate prefetch requests for strided access patterns having strides larger than a certain stride size. Another example is a spatial memory streaming (SMS)-based mechanism in which prefetch data from multiple evictions from the memory in the prefetch circuit is captured and used for SMS prefetching based on how well the prefetch data appears to match a spatial memory streaming pattern.

公开(公告)号：US12242855B2

公开(公告)日：2025-03-04

申请号：US18361212

申请日：2023-07-28

Applicant: Apple Inc.

Inventor： Aditya Kesiraju ,  Brett S. Feero ,  Nikhil Gupta ,  Viney Gautam

IPC: G06F9/38 ,  G06F9/30 ,  G06F9/48 ,  G06F9/52

Abstract: In an embodiment, a processor includes a buffer in an interface unit. The buffer may be used to accumulate coprocessor instructions to be transmitted to a coprocessor. In an embodiment, the processor issues the coprocessor instructions to the buffer when ready to be issued to the coprocessor. The interface unit may accumulate the coprocessor instructions in the buffer, generating a bundle of instructions. The bundle may be closed based on various predetermined conditions and then the bundle may be transmitted to the coprocessor. If a sequence of coprocessor instructions appears consecutively in a program, the rate at which the instructions are provided to the coprocessor (on average) at least matches the rate at which the coprocessor consumes the instructions, in an embodiment.

公开(公告)号：US20240036870A1

公开(公告)日：2024-02-01

申请号：US18361212

申请日：2023-07-28

Applicant: Apple Inc.

Inventor： Aditya Kesiraju ,  Brett S. Feero ,  Nikhil Gupta ,  Viney Gautam

IPC: G06F9/38 ,  G06F9/30 ,  G06F9/48 ,  G06F9/52

CPC classification number: G06F9/3814 ,  G06F9/30018 ,  G06F9/30043 ,  G06F9/3816 ,  G06F9/3877 ,  G06F9/4881 ,  G06F9/522

Abstract: In an embodiment, a processor includes a buffer in an interface unit. The buffer may be used to accumulate coprocessor instructions to be transmitted to a coprocessor. In an embodiment, the processor issues the coprocessor instructions to the buffer when ready to be issued to the coprocessor. The interface unit may accumulate the coprocessor instructions in the buffer, generating a bundle of instructions. The bundle may be closed based on various predetermined conditions and then the bundle may be transmitted to the coprocessor. If a sequence of coprocessor instructions appears consecutively in a program, the rate at which the instructions are provided to the coprocessor (on average) at least matches the rate at which the coprocessor consumes the instructions, in an embodiment.

公开(公告)号：US10970077B2

公开(公告)日：2021-04-06

申请号：US16437739

申请日：2019-06-11

Applicant: Apple Inc.

Inventor： Aditya Kesiraju ,  Mridul Agarawal ,  Nikhil Gupta

IPC: G06F9/38

Abstract: In an embodiment, a processor includes a load/store unit that executes load/store operations. The load/store unit may implement a two-level load queue. One of the load queues, referred to as a load retirement queue (LRQ), may track load operations from initial execution to retirement. Ordering constraints may be enforced using the LRQ. The other load queue, referred to as a load execution queue (LEQ), may track loads from initial execution to forwarding of data. Replay may be managed by the LEQ. In an embodiment, the LEQ may be smaller than the LRQ, which may permit the management of replay while still meeting timing requirements. Additionally, the larger LRQ may permit more load operations to be pending (not retired) in the processor, widening the window for out of order execution and supporting potentially higher processor performance.