公开(公告)号：US10331567B1

公开(公告)日：2019-06-25

申请号：US15435910

申请日：2017-02-17

Applicant: Apple Inc.

Inventor： Stephan G. Meier ,  Tyler J. Huberty ,  Nikhil Gupta ,  Francesco Spadini ,  Gideon Levinsky

IPC: G06F12/08 ,  G06F12/0862 ,  G06F12/12

Abstract: A prefetch circuit may include a memory, each entry of which may store an address and other prefetch data used to generate prefetch requests. For each entry, there may be at least one “quality factor” (QF) that may control prefetch request generation for that entry. A global quality factor (GQF) may control generation of prefetch requests across the plurality of entries. The prefetch circuit may include one or more additional prefetch mechanisms. For example, a stride-based prefetch circuit may be included that may generate prefetch requests for strided access patterns having strides larger than a certain stride size. Another example is a spatial memory streaming (SMS)-based mechanism in which prefetch data from multiple evictions from the memory in the prefetch circuit is captured and used for SMS prefetching based on how well the prefetch data appears to match a spatial memory streaming pattern.

公开(公告)号：US20240248844A1

公开(公告)日：2024-07-25

申请号：US18587289

申请日：2024-02-26

Applicant: Apple Inc.

Inventor： Francesco Spadini ,  Gideon Levinsky ,  Mridul Agarwal

IPC: G06F12/0804 ,  G06F9/30 ,  G06F9/38

CPC classification number: G06F12/0804 ,  G06F9/30043 ,  G06F9/3826 ,  G06F9/3834 ,  G06F2212/601

Abstract: In an embodiment, a processor implements a different atomicity size (for memory consistency order) than the operation size. More particularly, the processor may implement a smaller atomicity size than the operation size. For example, for multiple register loads, the atomicity size may be the register size. In another example, the vector element size may be the atomicity size for vector load instructions. In yet another example, multiple contiguous vector elements, but fewer than all the vector elements in a vector register, may be the atomicity size for vector load instructions.

公开(公告)号：US11914511B2

公开(公告)日：2024-02-27

申请号：US16907740

申请日：2020-06-22

Applicant: Apple Inc.

Inventor： Francesco Spadini ,  Gideon Levinsky ,  Mridul Agarwal

IPC: G06F12/0804 ,  G06F9/30 ,  G06F9/38

CPC classification number: G06F12/0804 ,  G06F9/30043 ,  G06F9/3826 ,  G06F9/3834 ,  G06F2212/601

Abstract: In an embodiment, a processor implements a different atomicity size (for memory consistency order) than the operation size. More particularly, the processor may implement a smaller atomicity size than the operation size. For example, for multiple register loads, the atomicity size may be the register size. In another example, the vector element size may be the atomicity size for vector load instructions. In yet another example, multiple contiguous vector elements, but fewer than all the vector elements in a vector register, may be the atomicity size for vector load instructions.

公开(公告)号：US20210397555A1

公开(公告)日：2021-12-23

申请号：US16907740

申请日：2020-06-22

Applicant: Apple Inc.

Inventor： Francesco Spadini ,  Gideon Levinsky ,  Mridul Agarwal

IPC: G06F12/0804 ,  G06F9/30

Abstract: In an embodiment, a processor implements a different atomicity size (for memory consistency order) than the operation size. More particularly, the processor may implement a smaller atomicity size than the operation size. For example, for multiple register loads, the atomicity size may be the register size. In another example, the vector element size may be the atomicity size for vector load instructions. In yet another example, multiple contiguous vector elements, but fewer than all the vector elements in a vector register, may be the atomicity size for vector load instructions.