公开(公告)号：US20240077932A1

公开(公告)日：2024-03-07

申请号：US18122410

申请日：2023-03-16

Applicant: Apple Inc.

Inventor： Talbott M. Houk ,  Wenxun Huang ,  Nikola Jovanovic ,  Floyd L. Dankert ,  Sanjay Pant ,  Alessandro Molari ,  Siarhei Meliukh ,  Nicola Florio ,  Ludmil N. Nikolov ,  Nathan F. Hanagami ,  Hartmut Sturm ,  Di Zhao ,  Chad L. Olson ,  John J. Sullivan ,  Seyedeh Maryam Mortazavi Zanjani ,  Tristan R. Hudson ,  Jay B. Fletcher ,  Jonathan A. Dutra

IPC: G06F1/3296 ,  G06F1/3212 ,  G06F1/3234

CPC classification number: G06F1/3296 ,  G06F1/3212 ,  G06F1/3278

Abstract: The present disclosure describes a system with a power management device, a wakeup circuit, a battery management device, and a connector. During a powered down mode of operation, the battery management device can provide, via the connector, a bias voltage to the wakeup circuit. In response to a wakeup switch being activated, the battery management device can provide a power supply (e.g., from a battery) to the power management device. Benefits of the wakeup circuit include (1) a reduction of battery consumption—and thus improving battery lifetime—when the electronic system is in a powered down mode of operation because the wakeup circuit has lower number of active components compared to other designs and (2) a non-complex wakeup circuit design because one or more existing connector interconnects between the power management device and the battery management device can be re-used during electronic system's powered down mode of operation.

公开(公告)号：US20160077579A1

公开(公告)日：2016-03-17

申请号：US14486491

申请日：2014-09-15

Applicant: Apple Inc.

Inventor： Manu Gulati ,  Tristan R. Hudson ,  Parin Patel ,  Fabien Faure

IPC: G06F1/32 ,  G06F1/20

CPC classification number: G06F1/3296 ,  G06F1/206 ,  G06F1/30 ,  G06F1/3275 ,  Y02D10/14 ,  Y02D10/16 ,  Y02D10/172

Abstract: In an embodiment, a system includes a power management unit (PMU), a non-volatile memory, a volatile memory, and a processor. The PMU may be configured to generate a power supply voltage, change a state of a status signal responsive to an event, and reduce a voltage level of the power supply voltage responsive to a predetermined period of time elapsing from detecting the event. The system may be configured to transition from a first to a second operating mode responsive to the change of the state of the status signal, and cancel pending commands to the non-volatile memory responsive to the transition to the second operating mode. The non-volatile memory may be configured to complete active commands prior the predetermined period of time elapsing.

Abstract translation: 在一个实施例中，系统包括电源管理单元（PMU），非易失性存储器，易失性存储器和处理器。 PMU可以被配置为产生电源电压，响应于事件改变状态信号的状态，并且响应于从检测到事件经过的预定时间段来降低电源电压的电压电平。 系统可以被配置为响应于状态信号的状态的改变而从第一操作模式转换到第二操作模式，并且响应于转换到第二操作模式而将待决命令取消到非易失性存储器。 非易失性存储器可以被配置为在经过预定时间段之前完成活动命令。

公开(公告)号：US12223110B1

公开(公告)日：2025-02-11

申请号：US17901470

申请日：2022-09-01

Applicant: Apple Inc.

Inventor： Denis G. Chen ,  Matthew T. Metzler ,  Eric M. Innis ,  Darya Amin-Shahidi ,  Shingo Yoneoka ,  Chi Kin Ho ,  Adriane S. Niehaus ,  Matthew N. Weege ,  Michael S. Weinstein ,  Tristan R. Hudson ,  Parin Patel ,  Jonathan A. Gordon

IPC: G06F3/01 ,  G06F3/041

Abstract: A software defined button includes a force sensor and a haptic output element. The button further includes an immutable logic core and a mutable logic core. The mutable logic core is configured to define one or more thresholds against which input received from the force sensor can be compared to determine whether a user input has been provided. The immutable logic core is configured to verify actual force input has been received when the mutable logic core signals that user input has been received. In response to receiving a verified force input, the haptic output element can be caused to be driven by one of the mutable or immutable logic cores to provide a haptic output to a user.

公开(公告)号：US09829966B2

公开(公告)日：2017-11-28

申请号：US14486491

申请日：2014-09-15

Applicant: Apple Inc.

Inventor： Manu Gulati ,  Tristan R. Hudson ,  Parin Patel ,  Fabien Faure

IPC: G06F1/32 ,  G06F1/20 ,  G06F1/30

CPC classification number: G06F1/3296 ,  G06F1/206 ,  G06F1/30 ,  G06F1/3275 ,  Y02D10/14 ,  Y02D10/16 ,  Y02D10/172

Abstract: In an embodiment, a system includes a power management unit (PMU), a non-volatile memory, a volatile memory, and a processor. The PMU may be configured to generate a power supply voltage, change a state of a status signal responsive to an event, and reduce a voltage level of the power supply voltage responsive to a predetermined period of time elapsing from detecting the event. The system may be configured to transition from a first to a second operating mode responsive to the change of the state of the status signal, and cancel pending commands to the non-volatile memory responsive to the transition to the second operating mode. The non-volatile memory may be configured to complete active commands prior the predetermined period of time elapsing.